Greg Tanaka

US Patent:

20130208112, Aug 15, 2013

Filed:

Dec 27, 2012

Appl. No.:

13/727605

Inventors:

Greg Lin Tanaka - Palo Alto CA, US
David Way Ng - Redwood City CA, US
Chengpeng Chen - Fremont CA, US
Dave Tahmoush - Adelphi MD, US
Derek Ma - Palo Alto CA, US

Assignee:

Eye Stalks Corporation - Palo Alto CA

International Classification:

H04N 7/18

US Classification:

348143

Abstract:

A device for visual monitoring comprises a mobile chipset disposed in a housing, at least one eyestalk attached to the housing and communicatively coupled to the mobile chipset, and mounting hardware affixed to the housing, the mounting hardware configured to secure the housing to a stationary structure. In one embodiment, the mobile chipset is configured to execute a set of program instructions in response to the device being connected to external power, including program instructions which, when executed by the mobile chipset, causes the device to take pictures in response to automatically generated triggers, and to automatically upload image data to a packet-based network for display and/or further processing. In a further embodiment, the device is configured to pre-process the image data, such as extracting relevant data for a specific application, before uploading the image data to the packt-based network for further process. In another embodiment, the device is configured to automatically upload image data to a social network site for sharing among authorised users of the cite.

US Patent:

D4258738, May 30, 2000

Filed:

Nov 25, 1998

Appl. No.:

D/097014

Inventors:

Curtis Lee Anderson - Pleasanton CA
Thomas L. Palecki - Pleasanton CA
Greg T. Tanaka - San Jose CA

Assignee:

SmartTouch Inc. - Berkeley CA

International Classification:

1402

US Classification:

D14100

US Patent:

61044180, Aug 15, 2000

Filed:

Apr 6, 1998

Appl. No.:

9/055566

Inventors:

Greg L. Tanaka - Sunnyvale CA
Sean Hsi-an Kuo - Saratoga CA
Kenneth Choy - Castro Valley CA
Michael M. Lee - San Jose CA
Gregory M. Stefanek - Mountain View CA

Assignee:

Silicon Magic Corporation - Sunnyvale CA

International Classification:

G06F 1316

US Classification:

345521

Abstract:

Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input signals that indicate accessing of at least one of the plurality of memory banks for a desired plurality of words of data. The method further includes splitting data access across the plurality of memory banks to allow parallel selection of an output from at least one of the plurality of memory banks as the desired plurality of words of the data, wherein latency of data access is amortized. A system aspect for improving data transfer from memory to a texture mapping unit includes a plurality of cache banks for storing texel data, a bank decode unit coupled to the plurality of cache banks for decoding a plurality of input signals indicative of selection of texel data from one or more of the plurality of banks, and selection control logic for receiving decoded address data from the bank decode unit and controlling selection of the plurality of cache banks to retrieve the texel data for output to the texture mapping unit.

US Patent:

56894724, Nov 18, 1997

Filed:

Oct 31, 1996

Appl. No.:

8/739868

Inventors:

Greg L. Tanaka - Sunnyvale CA
Sean H. Kuo - Saratoga CA

Assignee:

Silicon Magic Corporation - Cupertino CA

International Classification:

G11C 700

US Classification:

36523002

Abstract:

Apparatus, method, and system aspects for providing efficient accesses to memory in a computer system, the computer system including a controller, are described. Included in the aspects are a random access memory array having a plurality of rows and columns and coupled to the controller, and a column selection mechanism coupled to the memory array and the controller with the column selection mechanism being divided into predetermined portions for providing column selection signals to access chosen portions of a row in the memory array. Further included as the column selection mechanism is a multiplexer. In one embodiment, the multiplexer is divided into halves and provides separate selection signals for accessing upper word halves and lower word halves of the random access memory.

US Patent:

61667439, Dec 26, 2000

Filed:

Mar 19, 1997

Appl. No.:

8/820541

Inventors:

Greg L. Tanaka - Sunnyvale CA

Assignee:

Silicon Magic Corporation - Sunnyvale CA

International Classification:

G06T 1540

US Classification:

345422

Abstract:

Aspects for effectively improving the throughput in a rasterization pipeline for image rendering in a computer system are provided. A method aspect includes receiving data for a chosen number of pixels in a Z-test mechanism of the rasterization pipeline, performing Z-test determinations for the chosen number of pixels in a same clock cycle to achieve faster processing in the Z-test mechanism than other portions of the rasterization pipeline, and tagging the chosen number of pixels based upon the Z-test determinations to indicate pass/fail status for rendering. A circuit aspect includes at least one memory device for storing pixel data, a Z-test mechanism, the Z-test mechanism within the rasterization pipeline and coupled to the at least one memory device for determining a pass/fail rendering status for a plurality of pixels received in parallel from the at least one memory means, and a plurality of mechanisms forming a portion of the rasterization pipeline following the Z-test mechanism, the plurality of mechanisms for processing pixel data with a pass status sequentially.