Gregory Renaldo Allen

US Patent:

56542453, Aug 5, 1997

Filed:

Mar 23, 1993

Appl. No.:

8/036049

Inventors:

Gregory Lee Allen - Vancouver WA

Assignee:

Sharp Microelectronics Technology, Inc. - Camas WA
Sharp Kabushiki Kaisha - Osaka

International Classification:

H01L 21285
H01L 21465

US Classification:

438629

Abstract:

The invention provides a method and structure in which a nucleating species [54] is implanted through apertures [52] of a metal-phobic layer [40] into a support layer [17] and copper or a like metal is selectively grown at the implant site or sites. The implant support layer [17] is preferably composed of a material which inhibits diffusion therethrough of the copper or other like grown metal.

US Patent:

54299870, Jul 4, 1995

Filed:

Jan 25, 1993

Appl. No.:

8/008745

Inventors:

Gregory L. Allen - Vancouver WA

Assignee:

Sharp Microelectronics Technology, Inc. - Camas WA
Sharp Kabushiki Kaisha - Osaka

International Classification:

H01L 2144

US Classification:

437187

Abstract:

A method for forming interconnects in an integrated circuit chip which includes a plurality of active devices over which a layer of dielectric material is deposited. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines; (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper. In another aspect of the invention, a layer of silicon nitride may be provided over the conductive material.