Gregory Cowan

US Patent:

60165618, Jan 18, 2000

Filed:

Jun 18, 1998

Appl. No.:

9/099831

Inventors:

Fariborz F. Roohparvar - Cupertino CA
Allahyar Vahidi Mowlavi - Santa Clara CA
Mark A. Hawes - Boise ID
Gregory L. Cowan - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3128

US Classification:

714720

Abstract:

A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.

US Patent:

57870977, Jul 28, 1998

Filed:

Jul 22, 1996

Appl. No.:

8/681527

Inventors:

Fariborz F. Roohparvar - Cupertino CA
Allahyar Vahidi Mowlavi - Santa Clara CA
Mark A. Hawes - Boise ID
Gregory L. Cowan - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3128

US Classification:

371 215

Abstract:

A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.