Gregory Lynn Palmer

US Patent:

6473845, Oct 29, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/675021

Inventors:

Bryan Hornung - Plano TX
Michael L. Ziegler - Campbell CA
Michael K. Traynor - San Jose CA
Gregory S. Palmer - Plano TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1300

US Classification:

711165, 711202, 711162, 711221

Abstract:

In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.

US Patent:

6490668, Dec 3, 2002

Filed:

Dec 15, 2000

Appl. No.:

09/738697

Inventors:

Bryan Hornung - Plano TX
Gregory S Palmer - Plano TX
Paul F. Vogel - Garland TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711165, 711162

Abstract:

A system for moving checksums within memory utilizes a plurality of memory systems and a system manager. A first memory system has a first memory location that is correlated with a checksum indicator. The checksum indicator identifies the memory system that is storing the checksum of the value presently stored at the first location. The system manager dynamically moves the checksum to a destination memory location and updates the checksum indicator such that the checksum indicator identifies the memory system of the destination memory location. While the checksum is being moved, checksum updates may occur to the memory location from which the checksum was moved. Thus, after moving the checksum, the system manager updates the checksum with the value stored at the location from which the checksum was moved. As a result, the checksum stored in the checksum destination location should be sufficiently updated to enable data recovery.

US Patent:

6665830, Dec 16, 2003

Filed:

Jan 31, 2001

Appl. No.:

09/773124

Inventors:

Bryan Hornung - Plano TX
Gregory S Palmer - Plano TX
Paul F. Vogel - Garland TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 2900

US Classification:

714766, 711165, 714767

Abstract:

A system for building checksums efficiently builds a checksum of various data values that are stored in different memory units of a computer system. During the checksum build process, data stores to the memory locations storing the various data values are enabled, thereby enabling the checksum to be built without significantly impacting the performance of the computer system.

US Patent:

6876657, Apr 5, 2005

Filed:

Dec 14, 2000

Appl. No.:

09/737646

Inventors:

Tony M. Brewer - Plano TX, US
Michael K. Dugan - Richardson TX, US
Jim Kleiner - Dallas TX, US
Gregory S. Palmer - Plano TX, US
Paul F. Vogel - Garland TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

H04L012/28

US Classification:

370394, 370401, 370414, 370428

Abstract:

Hardware interconnected around multiple packet forwarding engines prepends sequence numbers to packets going into multiple forwarding engines through parallel paths, After processing by the multiple forwarding engines, packets are reordered using queues and a packet ordering mechanism, such that the sequence numbers are put back into their original prepended order. Exception packets flowing through the forwarding engines do not follow a conventional fast path, but are processed off-line and emerge from the forwarding engines out of order relative to fast path packets. These exception packets are marked, such that after they exit the forwarding engines, they are ordered among themselves independent of conventional fast path packets. Viewed externally, all exception packets are ordered across all multiple forwarding engines independent of the fast path packets.

US Patent:

6879559, Apr 12, 2005

Filed:

Oct 31, 2000

Appl. No.:

09/703043

Inventors:

Harry C. Blackmon - Plano TX, US
Tony M. Brewer - Plano TX, US
Harold W. Dozier - Dallas TX, US
Jim Kleiner - Dallas TX, US
Gregory S. Palmer - Plano TX, US
Keith W. Shaw - Plano TX, US
David Traylor - Richardson TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

H04L001/22

US Classification:

370225, 370216, 370227, 370228, 370392, 370471, 370473, 398 24, 398 83

Abstract:

Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds. Alternatively, protect line cards can routinely carry low priority traffic that is interruptible, allowing the protect line card to handle higher priority traffic previously carried by a failed working line card.

US Patent:

6894970, May 17, 2005

Filed:

Oct 31, 2000

Appl. No.:

09/703064

Inventors:

Harry C. Blackmon - Plano TX, US
Tony M. Brewer - Plano TX, US
Harold W. Dozier - Dallas TX, US
Jim Kleiner - Dallas TX, US
Gregory S. Palmer - Plano TX, US
Keith W. Shaw - Plano TX, US
David Traylor - Richardson TX, US
Dean E. Walker - Plano TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

H04L001/22
H04L012/26

US Classification:

370220, 370218, 370219, 370228, 3703951

Abstract:

Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.

US Patent:

6999411, Feb 14, 2006

Filed:

Jan 12, 2001

Appl. No.:

09/760027

Inventors:

Tony M. Brewer - Plano TX, US
Gregory S. Palmer - Plano TX, US
Keith W. Shaw - Plano TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

G01R 11/08

US Classification:

370220, 370221, 370461, 398 2, 398 6, 398 10

Abstract:

In a router with redundant central arbiters, a set of control processors (CPs) determines which arbiter is active, which is standby, and when to switch between them. In normal operation ingress ASICs issue requests to the active central arbiter ASIC and keep-alive requests cyclically once per chunk period to the passive arbiter ASIC, which then returns keep-alive grants through the same links to the ingress ASICs and sends standby configuration information to the optical switch ASICs. The arbiter ASICs pass a switch-over decision simultaneously to the optical switch ASICs and ingress ASICs, which empty all queues of outstanding requests, and then resend all of those requests to the new active central arbiter after all queues are empty, such that no router traffic is lost. Mechanisms ensure that during the transition the ASICs properly recognize which data links are healthy and which arbiter is active.

US Patent:

7002980, Feb 21, 2006

Filed:

Dec 19, 2000

Appl. No.:

09/740923

Inventors:

Tony M. Brewer - Plano TX, US
Jim Kleiner - Dallas TX, US
Gregory S. Palmer - Plano TX, US
Keith W. Shaw - Plano TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

H04L 12/28

US Classification:

370414, 370229, 370235, 709223, 709232

Abstract:

In a multi-QOS level queuing structure, packet payload pointers are stored in multiple queues and packet payloads in a common memory pool. Algorithms control the drop probability of packets entering the queuing structure. Instantaneous drop probabilities are obtained by comparing measured instantaneous queue size with calculated minimum and maximum queue sizes. Non-utilized common memory space is allocated simultaneously to all queues. Time averaged drop probabilities follow a traditional Weighted Random Early Discard mechanism. Algorithms are adapted to a multi-level QOS structure, floating point format, and hardware implementation. Packet flow from a router egress queuing structure into a single egress port tributary is controlled by an arbitration algorithm using a rate metering mechanism. The queuing structure is replicated for each egress tributary in the router system.