Gregory J Rausch

US Patent:

7443219, Oct 28, 2008

Filed:

Jan 4, 2007

Appl. No.:

11/649435

Inventors:

Gregory Jason Rausch - Plymouth MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03H 11/16

US Classification:

327231, 327235, 708290

Abstract:

A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.

US Patent:

7532053, May 12, 2009

Filed:

Jan 4, 2007

Appl. No.:

11/649434

Inventors:

Gregory Jason Rausch - Plymouth MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03H 11/16

US Classification:

327231, 327235, 708290

Abstract:

A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

US Patent:

8000073, Aug 16, 2011

Filed:

Mar 11, 2008

Appl. No.:

12/075400

Inventors:

Robert John Schuelke - Lakeville MN, US
Gregory J. Rausch - Minnetonka MN, US

Assignee:

Polar Semiconductor, Inc. - Bloomington MN

International Classification:

H02H 3/24

US Classification:

361 92

Abstract:

A current-mode under voltage lockout (UVLO) circuit provides an output signal that indicates to connected devices whether a connected power supply is sufficient (i. e. , of sufficient strength and stability) based on a comparison of a current that is proportional to the power supply and a reference current. The current-based UVLO circuit employs a reference current generator that is capable of providing a stable reference current and a voltage-to-current converter that provides a current proportional to the power supply voltage. A comparator compares the reference current to the current proportional to the power supply voltage and determines based on the magnitudes of the two currents whether the power supply voltage is sufficient or ‘good’ and generates an output signal indicating the status of the power supply voltage.

US Patent:

8085563, Dec 27, 2011

Filed:

Feb 12, 2009

Appl. No.:

12/378267

Inventors:

Michael J. Gaboury - Burnsville MN, US
Gregory J. Rausch - Minnetonka MN, US

Assignee:

Polar Semiconductor, Inc. - Bloomington MN

International Classification:

H02M 7/04

US Classification:

363 89, 363 80, 323222, 323285

Abstract:

A controller generates a drive signal for a converter circuit that includes an active component (i. e. , transistor) that is selectively controlled to convert a rectified input to direct current (DC) output. The controller employs an outer feedback loop (based on monitored output voltage of the converter circuit), an inner feedback loop (based on monitored AC input current drawn by the converter circuit), and a pulse width modulator (PWM) to generate the drive signals necessary to generate the desired DC output voltage and to provide power factor correction to the converter circuit. In particular, the inner feedback loop includes an amplifier and a fault protection and clamp circuit. The amplifier has a first input connected to receive a feedback signal representing the monitored AC input current, a second input, and an output that provides a current feedback signal to the PWM. The fault protection and clamp circuit is connected to monitor the voltage at the second input of the PWM and to detect fault conditions associated with the converter circuit, wherein in response to an over-voltage condition at the second input or a detected fault condition the fault protection and claim circuit clamps the current feedback signal provided to the second input of the PWM to a reference value and provides the reference value in feedback to either the first or second input of the amplifier.

US Patent:

8248040, Aug 21, 2012

Filed:

Nov 12, 2009

Appl. No.:

12/617662

Inventors:

Gregory J. Rausch - Minnetonka MN, US
Michael J. Gaboury - Burnsville MN, US
Shohei Osaka - Saitama, JP

Assignee:

Polar Semiconductor Inc. - Bloomington MN

International Classification:

G05F 1/70
G05F 3/16
G05F 1/00

US Classification:

323207, 323285, 323272, 323225

Abstract:

The present invention provides a method of controlling an interleaved power factor correction (PFC) circuit operating in a discontinuous conduction mode (DCM). The controller employs a normal mode of operation in which inductor currents in each PFC sub-circuit are estimated based on the monitored input voltage and monitored output voltage, and switching devices associated with each PFC sub-circuit are controlled to ensure DCM operation. As the input voltage increases, the OFF times of each PFC sub-circuit increase such that the inductor currents no longer overlap. In response, the controller activates a time-limiting mode (TLM) in which OFF time durations for each sub-circuit are based on the monitored sum of load currents as opposed to the monitored input voltage and monitored output voltage.

US Patent:

8248041, Aug 21, 2012

Filed:

Nov 12, 2009

Appl. No.:

12/617664

Inventors:

Gregory J. Rausch - Minnetonka MN, US
Michael J. Gaboury - Burnsville MN, US
Shohei Osaka - Saitama, JP

Assignee:

Polar Semiconductor Inc. - Bloomington MN

International Classification:

G05F 1/70
G05F 1/613

US Classification:

323207, 323272, 323299, 323 65

Abstract:

A controller provides frequency compression for an interleaved power factor correction (PFC) converter that determines the ON and OFF times of each switch associated with the PFC converter to prevent operating frequencies in the audible range. The controller includes a first circuit for generating an ON time current source having a magnitude related to an amplified error signal and the monitored input voltage, and a second circuit for generating an OFF time current source having a magnitude related to the ON time current source, the monitored input voltage, and the monitored output voltage. Gate drive circuitry provides gate drives signals to the switches of the interleaved PFC converter at a frequency determined by magnitudes of the ON time current source and the OFF time current source.

US Patent:

8476879, Jul 2, 2013

Filed:

Jan 27, 2010

Appl. No.:

12/657746

Inventors:

Michael J. Gaboury - Burnsville MN, US
Gregory J. Rausch - Minnetonka MN, US
Shohei Osaka - Saitama, JP

Assignee:

Polar Semiconductor, Inc. - Bloomington MN

International Classification:

G05F 1/70

US Classification:

323272, 323207, 323222

Abstract:

A method of controlling a power factor correction (PFC) converter having a first PFC sub-circuit and a second PFC sub-circuit determines when to transition the PFC converter between an interleaved mode and a saving energy mode (SEM). The method includes generating an amplified error signal based on a monitored output voltage of the PFC converter. The second PFC sub-circuit is disabled in response to the amplified error signal being less than a first threshold value and enabled in response to the amplified error signal exceeding a second threshold value.

US Patent:

20210052223, Feb 25, 2021

Filed:

May 7, 2020

Appl. No.:

16/869393

Inventors:

- Plymouth MN, US
Gregory J. Rausch - Minnetonka MN, US
Marcus A. Kramer - Circle Pines MN, US

International Classification:

A61B 5/00
A61B 5/1455

Abstract:

A device includes a digit probe, a plurality of optical elements, a processor, and a communication module. The digit probe has an interior surface and has an exterior surface. The interior surface is configured to engage a digit and the exterior surface is configured to engage a tissue site associated with the digit. The plurality of optical elements is coupled to at least one of the interior surface and the exterior surface. The plurality of optical elements includes at least one emitter and includes at least one detector. The processor is coupled to the plurality of optical elements. The processor is configured to generate a measure of arterial oxygenation corresponding to the digit and configured to generate a measure of regional oxygenation corresponding to the tissue site. The communication module is coupled to the processor. The communication module is configured to communicate the measure of arterial oxygenation and regional oxygenation with a remote device.