Gregory M Schaeffer

US Patent:

7398491, Jul 8, 2008

Filed:

May 26, 2006

Appl. No.:

11/420529

Inventors:

Gregory M. Schaeffer - Poughkeepsie NY, US
Alexander J. Suess - Hopewell Junction NY, US
David J. Hathaway - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6

Abstract:

A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.

US Patent:

7475372, Jan 6, 2009

Filed:

Jul 6, 2005

Appl. No.:

11/160701

Inventors:

Chandramouli V. Kashyap - Portland OR, US
Gregory Michael Schaeffer - Poughkeepsie NY, US
David J. Widiger - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 1, 716 2

Abstract:

A method for computing a Miller-factor compensated for peak noise provided. The method includes mapping at least two delays as function of at least two Miller-factors; determining an equation of the function; computing a peak noise; computing a peak delay resulting from the peak noise; and computing the compensated Miller-factor based on the equation and the peak delay. The function can be either a linear function or a non-linear function.

US Patent:

7685549, Mar 23, 2010

Filed:

Sep 14, 2007

Appl. No.:

11/855323

Inventors:

Debjit Sinha - Wappingers Falls NY, US
Soroush Abbaspour - Fishkill NY, US
Ayesha Akhter - Austin TX, US
Gregory M. Schaeffer - Poughkeepsie NY, US
David J. Widiger - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 13, 716 14, 703 16

Abstract:

A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.

US Patent:

7739640, Jun 15, 2010

Filed:

Jan 12, 2007

Appl. No.:

11/622979

Inventors:

Soroush Abbaspour - Fishkill NY, US
Gregory M. Schaeffer - Poughkeepsie NY, US
Chandramouli Visweswariah - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 4, 716 5

Abstract:

In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

US Patent:

7750648, Jul 6, 2010

Filed:

Mar 31, 2008

Appl. No.:

12/059275

Inventors:

Eric A. Foreman - Fairfax VT, US
Peter A. Habitz - Hinesburg VT, US
Mark R. Lasher - Colchester VT, US
William J. Livingstone - Underhill VT, US
Gregory M. Schaeffer - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 27/00

US Classification:

324677, 324654

Abstract:

A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.

US Patent:

8056035, Nov 8, 2011

Filed:

Jun 4, 2008

Appl. No.:

12/132636

Inventors:

Nathan C. Buck - Underhill VT, US
Brian M. Dreibelbis - Underhill VT, US
John P. Dubuque - Jericho VT, US
Eric A. Foreman - Fairfax VT, US
Peter A. Habitz - Hinesburg VT, US
David J. Hathaway - Underhill VT, US
Gregory M. Schaeffer - Poughkeepsie NY, US
Chandramouli Visweswariah - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716113, 716108

Abstract:

A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

US Patent:

20090210839, Aug 20, 2009

Filed:

Feb 14, 2008

Appl. No.:

12/031106

Inventors:

Nathan C. Buck - Underhill VT, US
John P. Dubuque - Jericho VT, US
Eric A. Foreman - Fairfax VT, US
Peter A. Habitz - Hinesburg VT, US
Kerim Kalafala - Rhinebeck NY, US
Gregory M. Schaeffer - Poughkeepsie NY, US
Chandramouli Visweswariah - Croton-on-Hudson NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6

Abstract:

A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin.

US Patent:

20210011980, Jan 14, 2021

Filed:

Jul 9, 2019

Appl. No.:

16/506746

Inventors:

- Armonk NY, US
Kerim Kalafala - Rhinebeck NY, US
Alexander Joel Suess - Hopewell Junction NY, US
Hemlata Gupta - Hopewell Junction NY, US
Gregory Schaeffer - Poughkeepsie NY, US

International Classification:

G06F 17/50

Abstract:

To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.