Gregory V Tarsy

US Patent:

53676874, Nov 22, 1994

Filed:

Jul 7, 1993

Appl. No.:

8/088418

Inventors:

Gregory Tarsy - Scotts Valley CA
Michael J. Woodard - Fremont CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 938

US Classification:

395700

Abstract:

A method and apparatus for optimizing cost-based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. Instruction scheduling is optimized by determining the optimal weights to be used by an apparatus for cost based heuristic instruction scheduling for a particular pipelined processor. The optimal weights are determined based on the lowest of the lowest costs incurred by different collections of interrelated weight sets. Each collection of interrelated weight sets comprises a randomly generated initial weight set and subsequent interrelated weight sets generated in a predetermined manner. The predetermined manner for generating subsequent weight sets facilitates rapid identification of the optimal weight set for a collection, and thereby rapid identification of the overall optimal weight set for the collections.

US Patent:

52029930, Apr 13, 1993

Filed:

Feb 27, 1991

Appl. No.:

7/661674

Inventors:

Gregory Tarsy - Scotts Valley CA
Michael J. Woodard - Fremont CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 945
G06F 938

US Classification:

395700

Abstract:

A method and apparatus for cost based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. The method and apparatus schedules instructions of an instruction block one at a time, based on the lowest total cost among all the current eligible free instructions. The total cost of each of the current eligible free instructions is computed based on the weighted sum of a plurality of cost heuristics. The cost heuristics used in the preferred embodiment comprise a resource dependency cost, a data dependency cost, a dependency wait cost, a dependent cycle cost, a floating point ratio cost, a store ratio cost and a floating point queue cost. Additionally, in the preferred embodiment, a number of the cost heuristics are modeled by a processor model. As a result, improved overall effectiveness in speeding up the execution time of an instruction block is achieved.