Guang S Chen from 5600 3Rd St APT 402, San Francisco, CA 94124, age 79, Phone: (415)8228320

Dynamic Power Load Line By Configuration
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US Patent:

20220335190, Oct 20, 2022
Filed:

Jul 1, 2022
Appl. No.:

17/856776
Inventors:

Guang Chen - Fremont CA, US
Yuet Li - Fremont CA, US
Archanna Srinivasan - San Jose CA, US
International Classification:

G06F 30/347
Abstract:

Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Circuits And Methods For Detecting Decreases In A Supply Voltage In An Integrated Circuit
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US Patent:

20210313989, Oct 7, 2021
Filed:

Jun 21, 2021
Appl. No.:

17/353549
Inventors:

- Santa Clara CA, US
Guang Chen - Fremont CA, US
Venu Kondapalli - San Jose CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 19/1778
H03K 21/08
Abstract:

An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

Interleaving Scheme For Increasing Operating Efficiency During High Current Events On An Integrated Circuit
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US Patent:

20190044514, Feb 7, 2019
Filed:

Dec 22, 2017
Appl. No.:

15/852814
Inventors:

- Santa Clara CA, US
Guang Chen - Fremont CA, US
Jun Pin Tan - Kepong, MY
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 19/003
H03K 19/177
H03K 19/00
Abstract:

An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.