Eby G. Friedman - Rochester NY, US Guoqing Chen - Folsom CA, US
Assignee:
University of Rochester - Rochester NY
International Classification:
G06F 17/10
US Classification:
703 2
Abstract:
A computer system for simulating performance of transmission lines, such as on-chip interconnects. The simulation uses direct extraction of poles, in contrast to conventional methods using poles obtained by a truncated transfer function. Using the directly extracted poles, far end response characteristic(s) can be determined to thereby aid in design of circuits using transmission lines. The far end response characteristic(s) that may be determined based on the directly extracted poles include, but are not necessarily limited to, frequency dependent effects, step response, ramp response, delay, 50% delay, rise time, 10% to 90% rise time, overshoot and normalized overshoot. A CAE tool designer and/or CAE tool user may decide how many pole pairs to directly extract to achieve a desired balance between computation resources required and resulting precision in the determination of far end response characteristic(s).
Amd Mar 2012 - Apr 2016
Smts Engineer
Higon Ic Design Mar 2012 - Apr 2016
Director and Principal Engineer of Physical Design
Intel Corporation Jul 2007 - Jan 2012
Senior Physical Design Engineer
University of Rochester May 2002 - May 2007
Research Assistant
Xerox Fuji Soft Interface Oct 1991 - Feb 2001
Research Worker, Staff Engineer, Group Leader
Education:
University of Rochester 2001 - 2007
Doctorates, Doctor of Philosophy
Tsinghua University 1998 - 2001
Master of Science, Masters
Tsinghua University 1993 - 1998
Bachelors, Bachelor of Science
Last Attended: Kinky University
Last Attended: Kinky University, Japan
Master of Science, Masters, Bachelors, Bachelor of Science
Skills:
C++ C Microsoft Excel Microsoft Office Windows Firmware Embedded Software Static Timing Analysis Cmos Spice Ic Microprocessors Eda Semiconductors Logic Synthesis Physical Design Asic Simulations Timing Closure Computer Architecture Low Power Design Dft Rtl Design Verilog Integrated Circuit Design Processors