Hao Tang

from Troy, NY

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Also known as:

Had Tang
Hae Tang

Phone and address:: 450 Fulton St, Troy, NY 12180
(518)6299377

Connected to:

Hao Tang Phones & Addresses

450 Fulton St, Troy, NY 12180 • (518)6299377
Rutland, VT
Loudonville, NY
Schenectady, NY
New Orleans, LA
Latham, NY
Metairie, LA
Worcester, MA
450 Fulton St, Troy, NY 12180 • (518)7525050

Work

Position:

Precision Production Occupations

Amazon

Basic Course of 3ds Max (1 DVD) (Chinese Edition)

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It gives systematic introduction to the basic functions of 3ds Max 2011 and how to create 3 D model, three-dimensional rendering, three-dimensional animation, and the method for special effect and operation skills. The book is well arranged in consideration of the learning features of beginners. The...

Author
Tan Xue Song, Yang Ming Chuan, Tang Hao

Binding
Paperback

Pages
293

Publisher
Posts and Telecom Press

ISBN #
7115258740

EAN Code
9787115258748

ISBN #
10

Face Processing and Applications to Distance Learning

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This special compendium provides a concise and unified vision of facial image processing. It addresses a collection of state-of-the-art techniques, covering the most important areas for facial biometrics and behavior analysis. These techniques also converge to serve an emerging practical application...

Author
Vuong Le, Pooya Khorrami, Usman Tariq, Hao Tang, Thomas Huang

Binding
Kindle Edition

Pages
120

Publisher
WSPC

ISBN #
8

曾国藩(注释本上中下)

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《曾国藩》是唐浩明长篇历史小说系列之一。唐浩明先生在尊重历史的前提下，倾注自己的情感，深刻把握住人物性格，写出了优秀的长篇历史小说《曾国藩》，将历史小说创作推向了高峰。在这套不同于以往版本的注释本中，将专业词汇：比如人物的字号、将领的官职以及清朝的兵制等等，均以脚注形式解释得比较清楚。注释本《曾国藩》，为历史上的曾国藩，文学上的《曾国藩》，以及写《曾国藩》的人共同织成的壮锦添上了一朵别致的花。

Author
唐浩明

Binding
Paperback

Publisher
YueLu Publishing House

ISBN #
755380374X

EAN Code
9787553803746

ISBN #
2

Shaolin martial arts secret research(Chinese Edition)

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Author
TANG HAO

Binding
Paperback

Publisher
Shanxi Science and Technology Press Pub. Date :200

ISBN #
7537729743

EAN Code
9787537729741

ISBN #
1

Resumes

Research Associate At Nera Economic Consulting

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Position:

Research Associate at NERA Economic Consulting

Location:

New York, New York

Industry:

Financial Services

Work:

NERA Economic Consulting - New York City since 2012
Research Associate
Trust Company of the West Jun 2011 - Aug 2011
Summer Analyst
Securities Industry and Financial Markets Association(SIFMA) May 2010 - Jul 2010
Summer Intern, Global Advocacy and Government Relations
Southern California Edison Nov 2009 - May 2010
Intern, Strategic Planning and Market Resource
Noah Private Wealth Management Jun 2009 - Jul 2009
Summer Intern

Education:

Pomona College 2008 - 2012
Bachelor of Arts (B.A.), Economics (Magna Cum Laude, The Brystine Prize For Finance) University of Oxford 2010 - 2010

Honor & Awards:

The Brystine Prize For Finance In Honor Of Gary Smith, 12 Magna Cum Laude, 12 Distinction in Senior Exercise, 12 Phi Beta Kappa Society Membership, 11 Class of 2012 Robert Day Scholar, 12 Pomona College Scholar, 09-12

Languages:

English
Chinese
French

Business

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Industry:

Financial Services

Work:

Business

Skills:

Business Analysis
Business Strategy
Management
Business Development
Project Management
Financial Analysis
Risk Management
Strategic Planning
Vendor Management
Strategy
Business Intelligence
Change Management
Banking
New Business Development
Process Improvement
Team Management
Analysis
Financial Modeling
Crm
Sdlc

Languages:

English

Hao Tang

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Hao Tang

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Hao Tang

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Work:

Yto Express Co., Limited
Student

Hao Tang

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Hao Tang

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Hao Tang

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Location:

United States

Name / Title

Company / Classification

Phones & Addresses

Mr. Hao Ji Tang
Owner

Imperial Art Group
8182795 Canada Inc.
Art Galleries. Dealers & Consultants

1430 Prince of Wales, P.O. Box 38094, Ottawa, ON K2C 1N0
(866)8867912

Hao Ji Tang
Owner

Imperial Art Group
Art Galleries · Dealers & Consultants

(866)8867912

Us Patents

Low Capacitance Low Rc Wrap-Around-Contact
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US Patent:

20220199787, Jun 23, 2022
Filed:

Dec 23, 2020
Appl. No.:

17/132980
Inventors:

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Jing Guo - Niskayuna NY, US
Hao Tang - Slingerlands NY, US
Cheng Chi - Jersey City NJ, US
International Classification:

H01L 29/417
H01L 29/40
H01L 29/45
H01L 29/66
H01L 29/786
H01L 29/08
Abstract:

A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.

Patterning Integration Scheme With Trench Alignment Marks
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US Patent:

20200350257, Nov 5, 2020
Filed:

May 1, 2019
Appl. No.:

16/400131
Inventors:

- Armonk NY, US
Hao Tang - Slingerlands NY, US
Dominik Metzler - Saratoga Springs NY, US
Cornelius Brown Peethala - Slingerlands NY, US
International Classification:

H01L 23/544
H01L 21/56
H01L 21/768
Abstract:

Methods are provided for patterning an active region formed in a semiconductor wafer. In one aspect, the methods generally include providing active regions and kerf regions between active regions in the semiconductor wafer, wherein the active regions and the kerf regions include a patterned dielectric layer, a metal conductor, and a liner layer between the dielectric layer and the metal conductor. An upper surface of the active regions and the kerf regions is planarized to form a planar surface. The metal conductor from the kerf regions is selectively removed to form a trench. An optically opaque layer is conformally deposited onto the semiconductor wafer to form a recessed alignment mark in the kerf regions. The active regions are then patterned using the recessed alignment mark in the kerf region.

Efficient Metal-Insulator-Metal Capacitor
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US Patent:

20200273947, Aug 27, 2020
Filed:

May 11, 2020
Appl. No.:

16/871935
Inventors:

- San Jose CA, US
Isabel C. Estrada-Raygoza - Albany NY, US
Hemanth Jagannathan - Niskayuna NY, US
Chi-Chun Liu - Altamont NY, US
Yann A.M. Mignot - Slingerlands NY, US
Hao Tang - Albany NY, US
Assignee:

Tessera, Inc. - San Jose CA
International Classification:

H01L 49/02
Abstract:

A capacitor includes a stack. The stack has a first metallic layer formed over a substrate, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. The first metallic layer has at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain.

Developer Critical Dimension Control With Pulse Development
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US Patent:

20200089188, Mar 19, 2020
Filed:

Nov 22, 2019
Appl. No.:

16/691731
Inventors:

- Armonk NY, US
Hao Tang - Slingerlands NY, US
Yongan Xu - San Jose CA, US
International Classification:

G05B 19/402
G03F 7/30
G03F 7/20
Abstract:

Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

Gate Contact Structure For A Transistor Device
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US Patent:

20190386107, Dec 19, 2019
Filed:

Aug 29, 2019
Appl. No.:

16/555734
Inventors:

- Grand Cayman, KY
Hao Tang - Slingerlands NY, US
Cheng Chi - Jersey City NJ, US
Daniel Chanemougame - Troy NY, US
Lars W. Liebmann - Halfmoon NY, US
Mark V. Raymond - Latham NY, US
International Classification:

H01L 29/417
H01L 21/768
H01L 29/66
H01L 21/285
H01L 23/535
H01L 29/78
H01L 29/45
Abstract:

One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

Gate Contact Structure For A Transistor
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US Patent:

20190378900, Dec 12, 2019
Filed:

Aug 22, 2019
Appl. No.:

16/548335
Inventors:

- Grand Cayman, KY
Hao Tang - Slingerlands NY, US
Cheng Chi - Jersey City NJ, US
Daniel Chanemougame - Troy NY, US
Lars W. Liebmann - Halfmoon NY, US
Mark V. Raymond - Latham NY, US
International Classification:

H01L 29/417
H01L 21/768
H01L 29/66
H01L 21/285
H01L 23/535
H01L 29/45
Abstract:

One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

Efficient Metal-Insulator-Metal Capacitor
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US Patent:

20180350896, Dec 6, 2018
Filed:

Aug 1, 2018
Appl. No.:

16/052161
Inventors:

- Armonk NY, US
Isabel C. Estrada-Raygoza - Albany NY, US
Hemanth Jagannathan - Niskayuna NY, US
Chi-Chun Liu - Altamont NY, US
Yann A.M. Mignot - Slingerlands NY, US
Hao Tang - Albany NY, US
International Classification:

H01L 49/02
Abstract:

Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.

Method And Structure For Minimizing Fin Reveal Variation In Finfet Transistor
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US Patent:

20180315642, Nov 1, 2018
Filed:

Jan 8, 2018
Appl. No.:

15/864248
Inventors:

- Armonk NY, US
Kangguo Cheng - Schenectady NY, US
Juntao Li - Cohoes NY, US
Hao Tang - Albany NY, US
International Classification:

H01L 21/762
H01L 29/78
H01L 29/66
H01L 21/311
H01L 21/3115
H01L 29/06
Abstract:

A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions are on a top surface of the liner layer on the substrate and includes a dielectric layer; and a doped region on the dielectric layer.

News

New computational chemistry techniques accelerate the prediction of molecules and materials

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hats more, their neural network model can extract much more information about a molecule than just its energy. In previous work, people have used multiple different models to assess different properties, says Hao Tang, an MIT PhD student in materials science and engineering. Here we use just one
Date: Jan 14, 2025
Category: Science
Source: Google

Into the unknown: NASA space laser provides answers to a rainforest canopy mystery

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"A key difference between GEDI and many other satellites is its measurement of three-dimensional canopy structure," said Hao Tang, professor in the Department of Geography at the National University of Singapore (NUS) and co-author on the paper.
Date: Jul 18, 2023
Category: Science
Source: Google

Twitter Now Lets Users Report Multiple Abusive Tweets

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"Behavior that crosses the line into abuse is against our rules and we want it to be easy for you to report it to us. So, today we're introducing an improvement to our reporting process: the ability to attach multiple Tweets to a single report," Hao Tang, a safety engineer at Twitter, says.
Date: Apr 26, 2016
Category: Sci/Tech
Source: Google

Twitter tweak allows reporting multiple abusive tweets at once

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"This update makes it easier for you to provide us with more information about the extent of abuse and reduces the time it takes to do so," wrote engineer Hao Tang in a blog post. "That added context often helps us investigate issues and get them resolved faster."
Date: Apr 26, 2016
Category: Sci/Tech
Source: Google

Twitter Takes Another Step to Crack Down on Abuse

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users could only report tweets individually, which made it difficult to fully convey an abusive situation. This update makes it easier for you to provide us with more information about the extent of abuse and reduces the time it takes to do so, Twitter safety engineer Hao Tang said in a blog post. Th
Date: Apr 25, 2016
Category: Sci/Tech
Source: Google

Twitter Lets You Flag Multiple Abusive Tweets at a Time

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"We want everyone on Twitter to feel safe expressing themselves," Twitter Safety Engineer Hao Tang wrote in a blog post Monday. "Behavior that crosses the line into abuseis against our rules and we want it to be easy for you to report it to us."
Date: Apr 25, 2016
Category: Sci/Tech
Source: Google