Haoran R Duan from Camas, WA, age 58

Modular Bonding Pad Structure And Method
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US Patent:

7274109, Sep 25, 2007
Filed:

Sep 23, 2005
Appl. No.:

11/234003
Inventors:

James R. Emmert - Corvallis OR, US
Charles Evans - Corvallis OR, US
Michael Alvin Rencher - Corvallis OR, US
Haoran Duan - Corvallis OR, US
Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:

H01L 23/48
US Classification:

257786, 257692, 257698, 257E2302, 257E2307, 257E23152
Abstract:

A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.

System And Method For Implementing Package Level Ip Preverification For System On Chip Devices
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US Patent:

7401315, Jul 15, 2008
Filed:

Nov 14, 2005
Appl. No.:

11/274572
Inventors:

Haoran Duan - Corvallis OR, US
Charles Evans - Corvallis OR, US
Michael Alvin Rencher - Corvallis OR, US
James R. Emmert - Corvallis OR, US
Assignee:

Avago Technologies General IP Pte Ltd - Singapore
International Classification:

G06F 17/50
H03K 17/693
US Classification:

716 16
Abstract:

A method for implementing package-level intellectual property (PLIP) preverification for system on chip (SOC) devices includes providing at least one externally connected intellectual property (IP) core with an SOC. A package generic unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein said package generic unit is pre-verified in silicon and independent of the specific packaging of the SOC. A package adaptation unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein the package adaptation unit is pre-verified in silicon and dependent upon the specific packaging of the SOC.

On-Chip Test Circuit And Method For Testing Of System-On-Chip (Soc) Integrated Circuits
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US Patent:

7484188, Jan 27, 2009
Filed:

Mar 15, 2006
Appl. No.:

11/377108
Inventors:

Haoran Duan - Corvallis OR, US
Charles Evans - Corvallis OR, US
Michael Alvin Rencher - Corvallis OR, US
James R. Emmert - Corvallis OR, US
Assignee:

Marvell International Technology Ltd. - Hamilton
International Classification:

G06F 17/50
US Classification:

716 4, 716 5
Abstract:

A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command includes an operation code component, data component(s), and expected time component. The received operation command is processed to supply test data to each of the IP cores being tested. Result data is received in response to the supplied test data from each of the IP cores being tested. The result data is processed and from the processed result data is generated a status data packet. The status data packet includes the operation code component and a status flag component and is provided on the input/output port.

Modular Bonding Pad Structure And Method
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US Patent:

7648903, Jan 19, 2010
Filed:

Aug 17, 2007
Appl. No.:

11/840387
Inventors:

James R. Emmert - Corvallis OR, US
Charles Evans - Corvallis OR, US
Michael Alvin Rencher - Corvallis OR, US
Haoran Duan - Corvallis OR, US
Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:

H01L 21/4763
US Classification:

438618, 438613, 257786, 257E23043, 257E2307, 257E23152, 257E23153, 257E23175
Abstract:

A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.