Haowei Wu

US Patent:

20100180249, Jul 15, 2010

Filed:

Jan 15, 2009

Appl. No.:

12/354703

Inventors:

Robert Rumsey - Saratoga CA, US
Richard Dolan - Pleasanton CA, US
Haowei Wu - San Jose CA, US

Assignee:

MICREL, INC. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 12

Abstract:

A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.