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Haowei Wu

age ~43

from Fremont, CA

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Also known as:
  • Wei Wu Hao
Phone and address:
34165 Cromwell Pl, Fremont, CA 94555
Related to:
Connected to:

Haowei Wu Phones & Addresses

  • 34165 Cromwell Pl, Fremont, CA 94555
  • San Jose, CA
  • Alameda, CA

Resumes

Haowei Wu Photo 1

Software Engineer Iii

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Location:
New York, NY
Industry:
Environmental Services
Work:
Tower Research Capital
Software Engineer Iii
Education:
Columbia University In the City of New York 2015 - 2016
Masters, Environmental Engineering China Agricultural University 2010 - 2014
Bachelors, Environmental Engineering China Agricultural University 2011 - 2013
Bachelors, Bachelor of Business Administration, Business Administration, Management, Business Administration and Management
Skills:
Water Resource Management
R
Public Speaking
Autocad
Wastewater Treatment
Matlab
Data Analysis
Environmental Impact Assessment
Deep Learning
Environmental Economics
Arcgis
Hadoop
Statistical Data Analysis
Microsoft Office
Apache Spark
Microsoft Excel
C++
Python
Research
Machine Learning
Statistics
Data Mining
Big Data Analytics
Haowei Wu Photo 2

Account Management

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Integrated Device Technology Inc since Aug 2010
Sr. Foundry Technology Engineer
Micrel Oct 2005 - Aug 2010
Device/Process Integration Engineer
NXP Semiconductors Jun 2004 - Jul 2004
Product Engineering Intern
Education:
University of Southern California 2004 - 2005
MSEE, Electrical Engineering University College London, U. of London 2000 - 2003
BEng, Electronic and Electrical Engineering
Skills:
Ic
Process Integration
Cmos
Semiconductors
Mixed Signal
Soc
Semiconductor Industry
Analog Circuit Design
Silicon
Product Engineering
Haowei Wu Photo 3

Haowei Wu

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Us Patents

  • Chip-Scale Package Conversion Technique For Dies

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  • US Patent:
    20100180249, Jul 15, 2010
  • Filed:
    Jan 15, 2009
  • Appl. No.:
    12/354703
  • Inventors:
    Robert Rumsey - Saratoga CA, US
    Richard Dolan - Pleasanton CA, US
    Haowei Wu - San Jose CA, US
  • Assignee:
    MICREL, INC. - San Jose CA
  • International Classification:
    G06F 17/50
  • US Classification:
    716 12
  • Abstract:
    A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.
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