Dan Nowlin - Hillsboro OR, US Hari Tadepalli - Phoenix AZ, US Paul Zurcher - Hillsboro OR, US
International Classification:
H04M003/00
US Classification:
455/420000, 455/041000, 455/557000, 455/066000
Abstract:
A method for switching the use of a shared set of wireless I/O devices between multiple computers. The method of one embodiment comprises receiving a wireless request at a first machine to switch control of a device to a second machine. Control of the device is relinquished at said first machine. A token is transferred from the first machine to the second machine. Wireless control of the device is established at the second machine.
Register Scheduling In Iterative Block Encryption To Reduce Memory Operations
Systems and methods encrypt data according to a multi-round, block encryption algorithm, In some embodiments, each round includes transforming data held in a group of registers of a processor register set and maintaining round output in the group of registers to use as input in a subsequent round. In some embodiments, the multi-round, block encryption algorithm is the Advanced Encryption Standard algorithm.
Partitioning Responsibility Between Link Manager And Host Controller Interface Firmware Modules In Wireless Systems
Jane Dashevsky - Beaverton OR, US Hari Tadepalli - Phoenix AZ, US
International Classification:
H04B007/00
US Classification:
455/517000, 455/524000
Abstract:
Tasks are distributed between link manager and host controller interface firmware to improve efficiency. In particular, the host controller interface firmware handles tasks that concern the overall state of the wireless device. Conversely, commands pertaining to each link between a local and remote device are processed by the link manager firmware.
Virtual Machine Migration While Maintaining Live Network Links
- Santa Clara CA, US Krishnamurthy Jambur Sathyanarayana - Shannon, IE Sean Harte - Limerick, IE Thomas Long - Shannon, IE Eliezer Tamir - Beit Shemesh, IL Hari K. Tadepalli - Gilbert AZ, US
International Classification:
G06F 9/455 H04L 29/08
Abstract:
Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.
Technologies For Securing Network Function Virtualization Images
- Santa Clara CA, US Weigang LI - Shanghai, CN Danny T. ZHOU - Shanghai, CN Junyuan WANG - Shanghai, CN Hari K. TADEPALLI - Gilbert AZ, US Rashmin N. PATEL - Chandler AZ, US
International Classification:
H04L 29/06 H04L 9/32 H04W 12/00
Abstract:
Technologies for securing a virtualization network function (VNF) image includes a security server to generate a wrapping cryptographic key to wrap a private key of the VNF image and replace the private key with the wrapped private key to secure the private key. During operation, the VNF image may be authenticated by a network function virtualization (NFV) server as needed. Additionally, the signature of the VNF image may be updated each time the VNF image is shutdown to ensure the continued authenticity of the VNF image.
5G Network Slicing With Distributed Ledger Traceability And Resource Utilization Inferencing
Various systems and methods for implementing an edge computing system to realize 5G network slices with blockchain traceability for informed 5G service supply chain are disclosed. A system configured to track network slicing operations includes memory and processing circuitry configured to select a network slice instance (NSI) from a plurality of available NSIs based on an NSI type specified by a client node. The available NSIs uses virtualized network resources of a first network resource provider. The client node is associated with the selected NSI. The utilization of the network resources by the plurality of available NSIs is determined using an artificial intelligence (AI)-based network inferencing function. A ledger entry of associating the selected NSI with the client node is recorded in a distributed ledger, which further includes a second ledger entry indicating allocations of resource subsets to each of the NSIs based on the utilization.
Kapil Sood - Portland OR, US Naveen Lakkakula - Chandler AZ, US Hari K. Tadepalli - Chandler AZ, US Lokpraveen Mosur - Gilbert AZ, US Rajesh Gadiyar - Chandler AZ, US Patrick Fleming - Portlaoise, IE
International Classification:
H04L 9/32 H04L 9/08 H04L 9/14 H04L 29/06
Abstract:
A security accelerator device stores a first credential that is uniquely associated with the individual security accelerator device and represents a root of trust to a trusted entity. The device establishes a cryptographic trust relationship with a client entity that is based on the root of trust, the cryptographic trust relationship being represented by a second credential. The device receives and store a secret credential of the client entity, which is received via communication secured by the second credential. Further, the device executes a cryptographic computation using the secret client credential on behalf of the client entity to produce a computation result.
Hardware Processors And Methods For Tightly-Coupled Heterogeneous Computing
- Santa Clara CA, US Pierre Laurent - Quin, IE Hari K. Tadepalli - Gilbert AZ, US Prasad M. Ghatigar - Shannon, IE T.J. O'Dwyer - Cashel, IE Serge Zhilyaev - Chandler AZ, US
International Classification:
G06F 15/80 G06F 9/38 G06F 13/16 G06F 13/40
Abstract:
Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
Humana
Director, Security Innovation
Encore Semi
Senior Design Verification Engineer
Seagate Technology Sep 1, 2014 - May 2016
Staff Verification Engineer
Lsi Corporation 2008 - Aug 2014
Staff Verification Engineer and Verification Lead
Intel Corporation Jan 2006 - Feb 2008
Verification Lead and Manager
Education:
University of Delaware 1991 - 1995
Doctorates, Doctor of Philosophy
Nagarjuna University 1987 - 1991
Bachelors, Communication, Electronics
Indian Institute of Technology, Madras 1980 - 1987
Masters, Master of Technology, Bachelors, Bachelor of Technology
Skills:
Vlsi Systemverilog Verilog Semiconductors Asic Debugging Soc Perl Embedded Systems Linux Virtualization Security Processors Product Management Strategy Enterprise Software Device Drivers Cryptography Firmware C++ Computer Architecture Wireless C Embedded Software Multithreading Trusted Platform Module Key Management and Hsm Trusted Computing Public Key Cryptography Intel Sgx Elliptic Curve Cryptography Secure Sockets Layer Ipsec Openssl Pkcs#11 Virtual Private Network Fips 140 2 Nist Standards X86 X86 Virtualization
Languages:
English Telugu Hindi
System And Security Architect At Intel Corporation
System and Security Architect at Intel Corporation
Location:
Phoenix, Arizona Area
Industry:
Computer Hardware
Work:
Intel Corporation since Jan 2013
System and Security Architect
Intel Jun 2009 - Dec 2012
System Architect
Broadcom Nov 2008 - May 2009
Principal System Architect
Intel May 2003 - Oct 2008
Performance Architect
Intel Feb 1996 - May 2003
Sr. Software Engineer
Education:
University of Delaware 1991 - 1995
Ph.D., Computer and Information Sciences
Indian Institute of Technology, Madras 1980 - 1987
B.Tech/M.Tech, Mech Engg/ Comp. Sc.
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