Helen R Maynard

US Patent:

8124487, Feb 28, 2012

Filed:

Dec 22, 2008

Appl. No.:

12/341489

Inventors:

Helen L. Maynard - North Reading MA, US
Vikram Singh - North Andover MA, US
Hans-Joachim L. Gossman - Summit NJ, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/336

US Classification:

438300, 257E2143

Abstract:

A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

US Patent:

8431495, Apr 30, 2013

Filed:

Jul 8, 2010

Appl. No.:

12/832160

Inventors:

Helen Maynard - North Reading MA, US
George Papasouliotis - North Andover MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/00

US Classification:

438785, 438 29, 438712, 438799, 257 98, 257194, 257410, 257E21482

Abstract:

An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.

US Patent:

8465909, Jun 18, 2013

Filed:

Nov 1, 2010

Appl. No.:

12/916993

Inventors:

Nicholas P. T. Bateman - Reading MA, US
Helen L. Maynard - North Reading MA, US
Benjamin B. Riordon - Newburyport MA, US
Christopher R. Hatem - Salisbury MA, US
Deepak Ramappa - Boston MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

G03F 7/20

US Classification:

430325

Abstract:

Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.

US Patent:

20090227061, Sep 10, 2009

Filed:

Mar 4, 2009

Appl. No.:

12/397596

Inventors:

Nicholas Bateman - Burlington MA, US
Atul Gupta - Beverly MA, US
Christopher Hatem - Salisbury MA, US
George Papasouliotis - North Andover MA, US
Helen Maynard - North Reading MA, US

International Classification:

H01L 31/18

US Classification:

438 57

Abstract:

Methods of controlling the diffusion of a dopant in a solar cell are disclosed. A second species is used in conjunction with the dopant to modify the diffusion region. For example, phosphorus and boron both diffuse by pairing with interstitial silicon atoms. Thus, by controlling the creation and location of these interstitials, the diffusion rate of the dopant can be controlled. In one embodiment, a heavier element, such as germanium, argon or silicon, is used to create interstitials. Because of the presence of these heavier elements, the dopant diffuses deeper into the substrate. In another embodiment, carbon is implanted. Carbon reduces the number of interstitials, and thus can be used to limit the diffusion of the dopant. In another embodiment, a lighter element, such as helium is used to amorphize the substrate. The crystalline-amorphous interface created limits diffusion of the dopant into the substrate.

US Patent:

20090278059, Nov 12, 2009

Filed:

Apr 23, 2009

Appl. No.:

12/428527

Inventors:

Helen Maynard - North Reading MA, US
George D. Papasouliotis - North Andover MA, US

International Classification:

H01J 37/08

US Classification:

25049221

Abstract:

A method and apparatus are described herein which allow the progression of delamination of a film to be monitored. An interferometer is used to detect the onset and progression of thin film delamination. By projecting one or more wavelengths at a surface, and measuring the reflectance of these projected wavelengths, it is possible to monitor the progression of the delamination process. Testing has shown that different stages of the delamination process produce different reflectance graphs. This information can be used to establish implantation parameters, or can be used as an in situ monitor. The same techniques can be used for other applications. For example, in certain implantation systems, such as PECVD, a film of material may developed on the walls of the chamber. The techniques described herein can be used to monitor this separation, and determine when preventative maintenance may be performed on the chamber.

US Patent:

20100279479, Nov 4, 2010

Filed:

May 1, 2009

Appl. No.:

12/434364

Inventors:

Christopher R. Hatem - Cambridge MA, US
Helen L. Maynard - North Reading MA, US
Deepak A. Ramappa - Cambridge MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/30

US Classification:

438300, 257E21211

Abstract:

A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.

US Patent:

20110039034, Feb 17, 2011

Filed:

Aug 11, 2009

Appl. No.:

12/538913

Inventors:

Helen Maynard - North Reading MA, US
George D. Papasouliotis - North Andover MA, US
Vikram Singh - North Andover MA, US
Christopher Hatem - Cambridge MA, US
Ludovic Godet - North Reading MA, US

International Classification:

C23C 14/14
C23C 14/00

US Classification:

427527, 427523

Abstract:

A method of depositing and crystallizing materials on a substrate is disclosed. In a particular embodiment, the method may include creating a plasma having deposition-related species and energy-carrying species. During a first time period, no bias voltage is applied to the substrate, and species are deposited on the substrate via plasma deposition. During a second time period, a voltage is applied to the substrate, which attracts ions to and into the deposited species, thereby causing the deposited layer to crystallize. This process can be repeated until an adequate thickness is achieved. In another embodiment, the bias voltage or bias pulse duration can be varied to change the amount of crystallization that occurs. In another embodiment, a dopant may be used to dope the deposited layers.

US Patent:

20110086501, Apr 14, 2011

Filed:

Oct 12, 2010

Appl. No.:

12/902250

Inventors:

George D. Papasouliotis - North Andover MA, US
Vikram Singh - North Andover MA, US
Heyun Yin - Saugus MA, US
Helen L. Maynard - North Reading MA, US
Ludovic Godet - North Reading MA, US

Assignee:

VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. - Gloucester MA

International Classification:

H01L 21/30

US Classification:

438514, 257E21211

Abstract:

A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.