Helen Louise Maynard

US Patent:

6541149, Apr 1, 2003

Filed:

Feb 29, 2000

Appl. No.:

09/514494

Inventors:

Helen Louise Maynard - Somerset NJ
Jeremy Patrick Meyers - Springfield NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01M 486

US Classification:

429 40, 429 41, 429 44, 427115, 216 43, 430314, 156 60

Abstract:

Improved micro fuel cells suitable for portable electrical devices are provided, and processes for forming such cells. In one embodiment of the invention, silicon substrates are used both as the gas delivery structure for the fuel and the oxidant, and as the current collectors. Such use of silicon is advantageous in that it becomes possible both to utilize micromachining and lithographic techniques to form the desired structures, e. g. , the gas delivery channels, and also to integrate the fuel cell with silicon-based control circuitry. Advantageously, the silicon substrates comprise both gas delivery tunnels and porous silicon gas diffusion regions formed over the tunnels in the surface of the substrate, i. e. , the porous regions over the gas delivery tunnels are integral with the silicon substrate. In another embodiment of the invention, a monolithic structure is employed.

US Patent:

6750495, Jun 15, 2004

Filed:

May 12, 1999

Appl. No.:

09/310388

Inventors:

Glenn B. Alers - Santa Cruz CA
Helen Louise Maynard - Somerset NJ
Daniel Joseph Vitkavage - Winter Garden FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27108

US Classification:

257296, 257301, 257310

Abstract:

A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor.

US Patent:

7279426, Oct 9, 2007

Filed:

Sep 22, 2005

Appl. No.:

11/162766

Inventors:

Habib Hichri - Poughkeepsie NY, US
Kimberly A. Larsen - Poughkeepsie NY, US
Helen L. Maynard - Hopewell Junction NY, US
Kevin S. Petrarca - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302

US Classification:

438700, 438424, 438444, 438706

Abstract:

The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

US Patent:

8124487, Feb 28, 2012

Filed:

Dec 22, 2008

Appl. No.:

12/341489

Inventors:

Helen L. Maynard - North Reading MA, US
Vikram Singh - North Andover MA, US
Hans-Joachim L. Gossman - Summit NJ, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/336

US Classification:

438300, 257E2143

Abstract:

A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

US Patent:

8431495, Apr 30, 2013

Filed:

Jul 8, 2010

Appl. No.:

12/832160

Inventors:

Helen Maynard - North Reading MA, US
George Papasouliotis - North Andover MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/00

US Classification:

438785, 438 29, 438712, 438799, 257 98, 257194, 257410, 257E21482

Abstract:

An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.

US Patent:

8465909, Jun 18, 2013

Filed:

Nov 1, 2010

Appl. No.:

12/916993

Inventors:

Nicholas P. T. Bateman - Reading MA, US
Helen L. Maynard - North Reading MA, US
Benjamin B. Riordon - Newburyport MA, US
Christopher R. Hatem - Salisbury MA, US
Deepak Ramappa - Boston MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

G03F 7/20

US Classification:

430325

Abstract:

Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.

US Patent:

20020004259, Jan 10, 2002

Filed:

Sep 22, 1999

Appl. No.:

09/401409

Inventors:

RUICHEN LIU - WARREN NJ, US
HELEN LOUISE MAYNARD - SOMERSET NJ, US

Assignee:

Lucent Technologies, Inc.

International Classification:

H01L021/44
H01L021/48
H01L021/50
H01L021/4763

US Classification:

438/118000

Abstract:

A process for fabricating a multi-layer interconnect in which an organic low-k material is formed over a topographic substrate. An insulator such as silicon dioxide is formed over the organic low-k material. The insulator is planarized. Contact holes or vias are then etched in the two-layer stack.

US Patent:

20020029853, Mar 14, 2002

Filed:

May 30, 2001

Appl. No.:

09/870968

Inventors:

Eric Hudson - Berkeley CA, US
Jaroslaw Winniczek - Daly City CA, US
Joel Cook - Pleasanton CA, US
Helen Maynard - New York NY, US

International Classification:

H01L021/3065

US Classification:

156/345000

Abstract:

Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.