Helmut U Puchner

US Patent:

6342429, Jan 29, 2002

Filed:

Dec 22, 1999

Appl. No.:

09/469579

Inventors:

Helmut Puchner - Santa Clara CA
Shih-Fen Huang - Wappingers Falls NY

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2176

US Classification:

438424, 438303

Abstract:

Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

US Patent:

6358806, Mar 19, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/896958

Inventors:

Helmut Puchner - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438308, 438931

Abstract:

A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon carbide channel layer on the substrate. A silicon layer is formed on top of the strained silicon carbide channel layer. A gate insulation layer is formed on top of the silicon layer and strained silicon carbide channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.

US Patent:

6413881, Jul 2, 2002

Filed:

Mar 9, 2000

Appl. No.:

09/521312

Inventors:

Sheldon Aronowitz - San Jose CA
John Haywood - Santa Clara CA
James P. Kimball - San Jose CA
Helmut Puchner - Santa Clara CA
Ravindra Manohar Kapre - San Jose CA
Nicholas Eib - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2131

US Classification:

438775, 438776, 438777

Abstract:

A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.

US Patent:

6455363, Sep 24, 2002

Filed:

Jul 3, 2000

Appl. No.:

09/609527

Inventors:

Helmut Puchner - Santa Clara CA
Gary K. Giust - Cupertino CA
Weiran Kong - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438223, 438224, 438227, 438228

Abstract:

A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

US Patent:

6472715, Oct 29, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/675109

Inventors:

Helmut Puchner - Santa Clara CA
Ruggero Castagnetti - San Jose CA
Weiran Kong - Sunnyvale CA
Lee Phan - Fremont CA
Franklin Duan - Sunnyvale CA
Steven Michael Peterson - Eagan MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2976

US Classification:

257371, 257376, 257387

Abstract:

An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0. 25 m SRAM design having one or more N wells of a conventional depth not exceeding about 0. 5 m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 m. The deep N well of the 0. 25 m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 m, and preferably at least about 2 m.

US Patent:

6486064, Nov 26, 2002

Filed:

Sep 26, 2000

Appl. No.:

09/670448

Inventors:

Helmut Puchner - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438689, 438699, 438766, 438914, 438957

Abstract:

A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode.

US Patent:

6504219, Jan 7, 2003

Filed:

Sep 21, 2001

Appl. No.:

09/960765

Inventors:

Helmut Puchner - Santa Clara CA
Shih-Fen Huang - Wappingers Falls NY

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 27095

US Classification:

257371, 372374, 372441, 438585, 438296

Abstract:

Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

US Patent:

6511925, Jan 28, 2003

Filed:

Oct 19, 2001

Appl. No.:

10/033164

Inventors:

Sheldon Aronowitz - San Jose CA
Vladimir Zubkov - Mountain View CA
Helmut Puchner - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438788, 438216, 438240, 438261, 438287, 438783

Abstract:

In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.