Helmuth R Litfin

US Patent:

54478766, Sep 5, 1995

Filed:

Sep 27, 1994

Appl. No.:

8/313471

Inventors:

James C. Moyer - San Jose CA
Martin J. Alter - Los Altos CA
Helmuth R. Litfin - Cupertino CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 21265

US Classification:

437 41

Abstract:

A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i. e. , having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

US Patent:

63074907, Oct 23, 2001

Filed:

Sep 30, 1999

Appl. No.:

9/410111

Inventors:

Helmuth Robert Litfin - San Jose CA
Anthony Joseph Becker - San Jose CA
Clyde Manford Brown - Cupertino CA

Assignee:

The Engineering Consortium, Inc. - Santa Clara CA

International Classification:

H03M 110

US Classification:

341121

Abstract:

A digital to analog converter has a decoder configured to select weighted decoding elements in a decoding network. The decoded outputs increase in steps by a mathematical progression as a function of the value of the input to the decoder. A calibration circuit adjusts the value of the digital input code received by the decoder to achieve a calibration function. In a programmable resistor embodiment, the value of the resistance selected by subsequent digital codes increases by a constant ratio. An adder is used to add an offset value to the digital input, thereby shifting the value of the resistance selected by the decoder to compensate for fabrication variances. A three terminal embodiment suitable for a form-C switch has a shorting switch to permit the programmable resistor to be switched from an extremely high resistance to an extremely low resistance.

US Patent:

54397642, Aug 8, 1995

Filed:

Jul 1, 1993

Appl. No.:

8/086481

Inventors:

Martin J. Alter - Los Altos CA
Lawrence R. Sample - San Jose CA
Hiu F. Ip - San Jose CA
Marty E. Garnett - Los Gatos CA
Helmuth R. Litfin - Cupertino CA

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

One embodiment of the invention includes multiple patterns on a single mask, where all the patterns on the single mask are used for forming a single product. In the preferred embodiment, each of four quadrants of a mask have a different process layer pattern, where each of the four patterns is associated with a different process layer for the same product. After exposure of the wafer using the mask, the mask is rotated 90. degree. for the next exposure step so that the mask pattern image for the next layer to be formed on the wafer will overlie the designated quadrant of the wafer which will contain the final product. Although, by using this technique, three-quarters of the wafer will be unusable, this partial waste of the wafer will be offset by the savings in mask costs with low volume production, in prototyping situations, and in product debugging. Using the above technique, conventional mask exposure machines may be used.

US Patent:

53550080, Oct 11, 1994

Filed:

Nov 19, 1993

Appl. No.:

8/155029

Inventors:

James C. Moyer - San Jose CA
Martin J. Alter - Los Altos CA
Helmuth R. Litfin - Cupertino CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 2910
H01L 2978
H01L 2348

US Classification:

257341

Abstract:

A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i. e. , having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

US Patent:

55170463, May 14, 1996

Filed:

Feb 6, 1995

Appl. No.:

8/384168

Inventors:

Michael R. Hsing - San Jose CA
Martin E. Garnett - Los Gatos CA
James C. Moyer - San Jose CA
Martin J. Alter - Los Altos CA
Helmuth R. Litfin - Cupertino CA

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

H01L 2978

US Classification:

257336

Abstract:

A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P. sup. + body contact regions, N. sup. + source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.