Hem C Neema

US Patent:

8074077, Dec 6, 2011

Filed:

Apr 12, 2007

Appl. No.:

11/786954

Inventors:

Hem C. Neema - Sunnyvale CA, US
Kumar Deepak - San Jose CA, US
Jimmy Zhenming Wang - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 12/14

US Classification:

713189, 713193

Abstract:

A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

US Patent:

8161436, Apr 17, 2012

Filed:

Oct 20, 2009

Appl. No.:

12/582596

Inventors:

Hem C. Neema - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716104, 716103

Abstract:

The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.

US Patent:

8265918, Sep 11, 2012

Filed:

Oct 15, 2009

Appl. No.:

12/579846

Inventors:

Hem C. Neema - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US
Kumar Deepak - San Jose CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 703 13

Abstract:

Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

US Patent:

8327311, Dec 4, 2012

Filed:

Jul 21, 2011

Appl. No.:

13/188407

Inventors:

Hem C. Neema - San Jose CA, US
Sonal Santan - San Jose CA, US
Kumar Deepak - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 11/22

US Classification:

716136, 716100

Abstract:

Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

US Patent:

8418095, Apr 9, 2013

Filed:

May 10, 2012

Appl. No.:

13/468927

Inventors:

Hem C. Neema - Sunnyvale CA, US
Sonal Santan - San Jose CA, US
Kumar Deepak - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716103, 716106

Abstract:

One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc. , for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

US Patent:

8447581, May 21, 2013

Filed:

Sep 15, 2009

Appl. No.:

12/559847

Inventors:

David Roth - San Francisco CA, US
Hem C. Neema - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 716104

Abstract:

During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.

US Patent:

8495539, Jul 23, 2013

Filed:

Jan 10, 2012

Appl. No.:

13/347301

Inventors:

Valeria Mihalache - Santa Clara CA, US
Kumar Deepak - San Jose CA, US
Hem C. Neema - San Jose CA, US
Sonal Santan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

US Patent:

8516413, Aug 20, 2013

Filed:

May 10, 2012

Appl. No.:

13/468933

Inventors:

Sandeep S. Deshpande - Longmont CO, US
Hem C. Neema - Sunnyvale CA, US
Valeria Mihalache - Santa Clara CA, US
Kumar Deepak - San Jose CA, US
Sonal Santan - San Jose CA, US
David K. Liddell - Longmont CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/45

US Classification:

716103

Abstract:

One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.