Heng Tang

US Patent:

7661058, Feb 9, 2010

Filed:

Apr 17, 2007

Appl. No.:

11/736386

Inventors:

Heng Tang - Sunnyvale CA, US
Zining Wu - Los Altos CA, US
Gregory Burd - San Jose CA, US
Pantas Sutardja - Los Gatos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714784, 714758, 714770

Abstract:

A Redundant Array of Inexpensive Disks (RAID) controller comprises a RAID error correction code (ECC) encoder module that receives data for storage and that generates code words for data drives and one or more parity drives, which have physical locations. The code words are generated based on the data and a cyclic code generator polynomial. The logical locations correspond to index positions in the cyclic code generator polynomial. A mapping module maps the physical locations of the data and parity drives to the logical locations. When one of the data drives is removed, the mapping and RAID ECC encoder modules do not modify the map.

US Patent:

7774675, Aug 10, 2010

Filed:

Jul 5, 2006

Appl. No.:

11/481141

Inventors:

Adina Matache - Mounatin View CA, US
Heng Tang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Aditya Ramamoorthy - Santa Clara CA, US
Jun Xu - Milpitas CA, US
Zining Wu - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714755, 714786, 714788, 714763, 714762, 714801, 370206

Abstract:

A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

US Patent:

7782232, Aug 24, 2010

Filed:

Aug 6, 2008

Appl. No.:

12/187160

Inventors:

Xueshi Yang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Heng Tang - Sunnyvale CA, US
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H03M 13/00

US Classification:

341 94, 714755

Abstract:

Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

US Patent:

7840878, Nov 23, 2010

Filed:

Feb 27, 2007

Appl. No.:

11/711286

Inventors:

Heng Tang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Soichi Isono - Kanagawa, JP
Son Hong Ho - Los Altos CA, US
Vincent Wong - Fremont CA, US
Zining Wu - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 29/00
H03M 13/00

US Classification:

714770, 714769, 714755

Abstract:

A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.

US Patent:

7962827, Jun 14, 2011

Filed:

Oct 30, 2006

Appl. No.:

11/589532

Inventors:

Heng Tang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Zining Wu - Los Altos CA, US
Panu Chaichanavong - Mountain View CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H03M 13/00

US Classification:

714755

Abstract:

The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

US Patent:

7978100, Jul 12, 2011

Filed:

Aug 23, 2010

Appl. No.:

12/861693

Inventors:

Xueshi Yang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Heng Tang - Sunnyvale CA, US
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H03M 13/00

US Classification:

341 94, 714782, 714784

Abstract:

Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

US Patent:

8032812, Oct 4, 2011

Filed:

Oct 4, 2007

Appl. No.:

11/867356

Inventors:

Xueshi Yang - Sunnyvale CA, US
Zining Wu - Los Altos CA, US
Heng Tang - Sunnyvale CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H03M 13/00

US Classification:

714755, 714758

Abstract:

A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.

US Patent:

8036377, Oct 11, 2011

Filed:

Dec 12, 2007

Appl. No.:

11/955088

Inventors:

Tze Lei Poo - Sunnyvale CA, US
Siu-Hung Fred Au - Fremont CA, US
Gregory Burd - San Jose CA, US
David Geddes - Fremont CA, US
Heng Tang - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04L 9/00

US Classification:

380 28, 380 29, 380 44, 708233, 708492

Abstract:

The disclosure provides a hardware architecture for encryption and decryption device. The hardware architecture can improve the encryption and decryption data rate by using parallel processing, and pipeline operation. Further, the hardware architecture can save footprint by sharing hardware components. Additionally, the hardware architecture can be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager that is configured to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit that is configured to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit that is configured to encrypt a second portion of the array of data blocks into a second portion of encrypted data blocks based on corresponding tweaking values and the data encryption key, and a data block combiner that is configured to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks into an array of encrypted data blocks.