Hengfu F Hsu

US Patent:

7086024, Aug 1, 2006

Filed:

Jun 1, 2003

Appl. No.:

10/452848

Inventors:

Hengfu Hsu - Cupertino CA, US
Steven Teig - Menlo Park CA, US
Akira Fujimura - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 8, 716 12, 716 13, 716 14

Abstract:

A method for defining and producing a power grid structure of an IC having diagonal power and ground stripes. Stripes are placed in a 45 or 135 diagonal direction in relation to an IC layout's x-coordinate axis so that the stripes will be placed in a 45 or 135 diagonal direction, respectively, in relation to the bottom boundary of the resulting IC. The diagonal power and ground stripes are beneficial to diagonal signal wiring. The stripes may be placed across one layer of the IC or across more than one layer of the IC. The diagonal power stripes may have varying widths and/or varying spacing widths on a layer of the IC. The diagonal ground stripes may have varying widths and/or varying spacing widths on a layer of the IC.

US Patent:

7272803, Sep 18, 2007

Filed:

Jun 1, 2003

Appl. No.:

10/452189

Inventors:

Hengfu Hsu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 3, 716 12

Abstract:

A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45 or 135 diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.

US Patent:

7480887, Jan 20, 2009

Filed:

Jan 23, 2006

Appl. No.:

11/339330

Inventors:

Hengfu Hsu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 13, 716 8, 716 9, 716 10, 716 11, 716 12, 716 14

Abstract:

A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to determine dimensions and locations of power grid components for each IC layer using a power grid formula, an objective for the power grid formula, a set of constraints, and a set of parameters. The method also includes processes of a power grid router, power grid verifier, and global signal router that are used iteratively with processes of the power grid planner to continually refine the dimensions and locations of the power grid components until the power grid structure meets design constraints and until global signal routing is successful on each layer of the IC.

US Patent:

7631283, Dec 8, 2009

Filed:

Jul 19, 2007

Appl. No.:

11/780459

Inventors:

Hengfu Hsu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 13, 716 8, 716 9, 716 10, 716 11, 716 12, 716 14

Abstract:

A method for producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45 or 135 diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.

US Patent:

8245172, Aug 14, 2012

Filed:

Nov 2, 2009

Appl. No.:

12/611116

Inventors:

Hengfu Hsu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716120, 716118, 716119, 716126, 716130, 716133, 716135

Abstract:

A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45 or 135 diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.

US Patent:

7003748, Feb 21, 2006

Filed:

Jun 1, 2003

Appl. No.:

10/452100

Inventors:

Hengfu Hsu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 8, 716 9, 716 10, 716 11, 716 12, 716 13, 716 14

Abstract:

A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to determine dimensions and locations of power grid components for each IC layer using a power grid formula, an objective for the power grid formula, a set of constraints, and a set of parameters. The method also includes processes of a power grid router, power grid verifier, and global signal router that are used iteratively with processes of the power grid planner to continually refine the dimensions and locations of the power grid components until the power grid structure meets design constraints and until global signal routing is successful on each layer of the IC.