Henry Jyhyeu Chang

Address:

7907 Canoe Ln, Las Vegas, NV 89145

VIN:

1FMYU02Z97KA52224

Make:

FORD

Model:

ESCAPE

Year:

2007

US Patent:

6428719, Aug 6, 2002

Filed:

Jan 19, 2000

Appl. No.:

09/487454

Inventors:

Xuehua Wu - Union City CA
Wensen Li - Fremont CA
Si-Tuan Lam - San Jose CA
Henry C. Chang - San Jose CA
Kochan Ju - Fremont CA

Assignee:

Headway Technologies, Inc. - Milpitas CA

International Classification:

C23F 100

US Classification:

216105, 216 22

Abstract:

Write head coils for magnetic disk systems are commonly formed through electroplating onto a seed layer in the presence of a photoresist mask. It is then necessary to remove the seed layer everywhere except under the coil itself. The present invention achieves this through etching in a solution of ammonium persulfate to which has been added the complexing agent 1,4,8,11 tetraazundecane. This suppresses the reduction of Cu to Cu, thereby increasing the dissolution rate of copper while decreasing that of nickel-iron. Two ways of implementing this are describedâadding the complexing agent directly to the ammonium persulfate and introducing the 1,4,8,11 tetraazundecane through a dipping process that precedes conventional etching in the ammonium persulfate.

US Patent:

6434814, Aug 20, 2002

Filed:

Dec 16, 1998

Appl. No.:

09/212724

Inventors:

Henry C. Chang - San Jose CA
Cherngye Hwang - San Jose CA
Robert Otto Schwenker - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11B 5127

US Classification:

2960314, 2960307, 2960312, 2960317, 2960318, 360319, 360327, 216 22, 216 66

Abstract:

A method of making a magnetic head that has a read head with a track width includes the steps of depositing a read track width defining material layer on a read sensor material layer; forming a bi-layer photoresist mask on the read track width defining material layer that masks a read track width defining layer portion of the read track width defining material layer; removing by reactive ion etching (RIE) a portion of the read track width defining material layer not masked by the photoresist mask to form the read track width defining layer portion with exposed first and second side edges that are spaced apart a distance equal to the track width; removing by ion milling a first portion of the read sensor material layer not masked by the read track width defining layer portion to form a second portion of the read sensor material layer with exposed first and second side edges that have a width equal to the track width; depositing hard bias and lead material layers on the photoresist mask in contact with the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion; and removing the photoresist mask, thereby lifting off a portion of the hard bias and lead material layers leaving first and second hard bias and lead layers connected to the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion.

US Patent:

6567957, May 20, 2003

Filed:

Jan 4, 2001

Appl. No.:

09/754550

Inventors:

Henry Chang - Sunnyvale CA
Larry Cooke - Los Gatos CA
Merrill Hunt - Escondido CA
Wuudiann Ke - Cupertino CA
Christopher K. Lennard - Sunnyvale CA
Grant Martin - Pleasanton CA
Peter Paterson - Mission Viejo CA
Khoan Truong - Milpitas CA
Kumar Venkatramani - Saratoga CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 716 1

Abstract:

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designers experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designers experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

US Patent:

6519118, Feb 11, 2003

Filed:

Mar 11, 2002

Appl. No.:

10/094913

Inventors:

Henry C. Chang - San Jose CA
Cherngye Hwang - San Jose CA
Robert Otto Schwenker - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11B 5127

US Classification:

360317

Abstract:

A read track width defining layer is employed for defining first and second side edges of a read sensor. The read track width defining layer preferably remains in the head to planarize the read head at first and second hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer. The subtractive process is selective to the read track width defining layer over a read sensor material layer therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

US Patent:

6574778, Jun 3, 2003

Filed:

Jan 4, 2001

Appl. No.:

09/754725

Inventors:

Henry Chang - Sunnyvale CA
Larry Cooke - Los Gatos CA
Merrill Hunt - Escondido CA
Wuudiann Ke - Cupertino CA
Christopher K. Lennard - Sunnyvale CA
Grant Martin - Pleasanton CA
Peter Paterson - Mission Viejo CA
Khoan Truong - Milpitas CA
Kumar Venkatramani - Saratoga CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 1, 716 4

Abstract:

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designers experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designers experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

US Patent:

6594800, Jul 15, 2003

Filed:

Jan 4, 2001

Appl. No.:

09/754559

Inventors:

Henry Chang - Sunnyvale CA
Larry Cooke - Los Gatos CA
Merrill Hunt - Escondido CA
Wuudiann Ke - Cupertino CA
Christopher K. Lennard - Sunnyvale CA
Grant Martin - Pleasanton CA
Peter Paterson - Mission Viejo CA
Khoan Truong - Milpitas CA
Kumar Venkatramani - Saratoga CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 1, 716 4, 716 11

Abstract:

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designers experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designers experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

US Patent:

6629293, Sep 30, 2003

Filed:

Feb 23, 2001

Appl. No.:

09/754466

Inventors:

Henry Chang - Sunnyvale CA
Larry Cooke - Los Gatos CA
Merrill Hunt - Escondido CA
Wuudiann Ke - Cupertino CA
Christopher K. Lennard - Sunnyvale CA
Grant Martin - Pleasanton CA
Peter Paterson - Mission Viejo CA
Khoan Truong - Milpitas CA
Kumar Venkatramani - Saratoga CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4

Abstract:

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designers experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designers experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

US Patent:

6631470, Oct 7, 2003

Filed:

Mar 23, 2001

Appl. No.:

09/754642

Inventors:

Henry Chang - Sunnyvale CA
Larry Cooke - Los Gatos CA
Merrill Hunt - Escondido CA
Wuudiann Ke - Cupertino CA
Christopher K. Lennard - Sunnyvale CA
Grant Martin - Pleasanton CA
Peter Paterson - Mission Viejo CA
Khoan Truong - Milpitas CA
Kumar Venkatramani - Saratoga CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

713 3

Abstract:

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designers experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designers experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.