Henry R Farmer

US Patent:

6856270, Feb 15, 2005

Filed:

Jan 29, 2004

Appl. No.:

10/768835

Inventors:

Henry R. Farmer - Colchester VT, US
David E. Lackey - Jericho VT, US
Steven F. Oakland - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M001/38

US Classification:

341161, 711169

Abstract:

A pipeline array includes a register, a pipeline clock input, and Narrow Pulse Triggered Latches (NPTL) stages connected in series. Each NPTL stage includes a Latch Pulse Generator (LPG) and a parallel set of single latches clocked by the LPG. The latches provide the parallel data input and the parallel data output of the stage. Each LPG provides a narrow latch clock pulse in response to a Pipeline Clock Pulse (PCP) supplied to the register and the last stage of latches. Each PCP arrives at each preceding LPG in the array after a delay provided by intervening time delay units. The delays increase for each preceding stage with the least delay at the penultimate stage and with the greatest delay at the first stage. The data input of the first stage is connected to the output of the register. The data input of the each of other stage is connected to the data output of the preceding stage in the array.

US Patent:

7240266, Jul 3, 2007

Filed:

Feb 18, 2005

Appl. No.:

10/906407

Inventors:

Henry R. Farmer - Colchester VT, US
Gary D. Grise - Colchester VT, US
David W. Milton - Underhill VT, US
Mark R. Taylor - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714731, 714727, 714707, 713400, 713500, 326 93, 327291

Abstract:

When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.

US Patent:

20060248417, Nov 2, 2006

Filed:

Apr 28, 2005

Appl. No.:

10/908123

Inventors:

Henry Farmer - Colchester VT, US
Gary Grise - Colchester VT, US
David Milton - Underhill VT, US
Steven Oakland - Colchester VT, US
Mark Taylor - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/28

US Classification:

714724000

Abstract:

A clock selection circuit selectively passes one or more clocks into portions of an integrated circuit for testing. In one mode, the selection circuit passes a functional clock into a section of logic for an at speed test under test program control. In another mode, the selection circuit passes a clock other than the functional clock, such at a reduced frequency, in a test mode.

US Patent:

55722091, Nov 5, 1996

Filed:

Aug 16, 1994

Appl. No.:

8/291694

Inventors:

Henry R. Farmer - Colchester VT
Anne A. Wilson - Waterbury VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 730

US Classification:

341 67

Abstract:

A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes a history RAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history RAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, an address of the matching stored data element is generated. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The decompression apparatus also includes a history RAM unit for storing received data elements and includes a circuit for receiving a compression token and determining the storage addresses of the next data element from the length and address information contained in the token. The apparatus can identify the next address at high speed by a parallel processing using the predetermined length categories.