Henry Hy Yu

US Patent:

6463506, Oct 8, 2002

Filed:

Apr 29, 2000

Appl. No.:

09/562592

Inventors:

Curtis R. McAllister - Sunnyvale CA
Robert C. Douglas - Santa Clara CA
Henry Yu - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711118, 711 3, 711145, 711144

Abstract:

A memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to each data line stored in memory, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i. e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i. e. , the usable bit positions following inclusion of all of the cache tag bits.

US Patent:

6480990, Nov 12, 2002

Filed:

May 1, 2000

Appl. No.:

09/561725

Inventors:

Nolan David Sharp - Santa Clara CA
Henry C. Yu - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 8, 716 2, 716 9, 716 11, 716 14

Abstract:

An application specific integrated circuit (ASIC) and method of manufacture. The ASIC includes a substrate layer, at least one metal layer and an operational block. The metal layer is formed above the substrate layer. The operational block is formed in the substrate layer and the metal layer, and is definable by a two-dimensional boundary. The operational block includes a plurality of operational logic gates, a first subgroup of spare logic gates, a second subgroup of spare logic gates, operational wiring and spare gate wiring. The operational logic gates, the first subgroup and the second subgroup are formed on the substrate layer, with the first subgroup being spaced from the second subgroup. The operational wiring is routed into the metal layer and interconnects the operational logic gates to configure the operational block to perform a desired operation. The spare gate wiring is similarly routed into the metal layer.

US Patent:

7028150, Apr 11, 2006

Filed:

Aug 23, 2002

Appl. No.:

10/226418

Inventors:

Curtis R. McAllister - Sunnyvale CA, US
Robert C. Douglas - Santa Clara CA, US
Henry Yu - San Jose CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

711156, 711129, 711141, 711144, 711170, 714766, 714768, 714777

Abstract:

A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

US Patent:

D532783, Nov 28, 2006

Filed:

Sep 29, 2004

Appl. No.:

29/214276

Inventors:

Henry Jay Yu - Fremont CA, US

Assignee:

Authenex, Inc. - Hayward CA

International Classification:

1402

US Classification:

D14356

US Patent:

7735050, Jun 8, 2010

Filed:

Jun 13, 2006

Appl. No.:

11/452677

Inventors:

Henry Yu - Palo Alto CA, US
Darren Zacher - Calgary, AB T2G 2Z6, CA
Mandar Chitnis - Pleasanton CA, US
Varad Joshi - Portland OR, US
Anil Khanna - Beaverton OR, US

International Classification:

G06F 17/50

US Classification:

716 18, 716 2

Abstract:

Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

US Patent:

8555223, Oct 8, 2013

Filed:

Apr 12, 2012

Appl. No.:

13/445832

Inventors:

Henry Yu - Palo Alto CA, US
Joshua Baudhuin - Portland OR, US
Timothy Rosek - Gibsonia PA, US
Hui Xu - Wexford PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

US Patent:

8595662, Nov 26, 2013

Filed:

Apr 12, 2012

Appl. No.:

13/445832

Inventors:

Henry Yu - Palo Alto CA, US
Joshua Baudhuin - Portland OR, US
Timothy Rosek - Gibsonia PA, US
Hui Xu - Wexford PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

US Patent:

8645902, Feb 4, 2014

Filed:

Apr 12, 2012

Appl. No.:

13/445847

Inventors:

Henry Yu - Palo Alto CA, US
Jeffrey Markham - San Jose CA, US
Min Cao - San Ramon CA, US
Roland Ruehl - San Carlos CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 15/04

US Classification:

716139, 716 55

Abstract:

Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.