Herman V Chang

US Patent:

6380759, Apr 30, 2002

Filed:

Jul 26, 2000

Appl. No.:

09/626094

Inventors:

Om P. Agrawal - Los Altos CA
Herman M. Chang - Cupertino CA
Bradley A. Sharpe-Geisler - San Jose CA
Giap H. Tran - San Jose CA

Assignee:

Vantis Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38

Abstract:

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGBs) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUTs) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUTs and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section.

US Patent:

6526558, Feb 25, 2003

Filed:

Dec 8, 2000

Appl. No.:

09/733878

Inventors:

Om P. Agrawal - Los Altos CA
Bradley A. Sharpe-Geisler - San Jose CA
Herman M. Chang - Cupertino CA
Bai Nguyen - San Jose CA
Giap H. Tran - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 1750

US Classification:

716 16, 326 38

Abstract:

A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGBs make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e. g. , feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

US Patent:

6590415, Jul 8, 2003

Filed:

Apr 23, 2001

Appl. No.:

09/841209

Inventors:

Om P. Agrawal - Los Altos CA
Bradley A. Sharpe-Geisler - San Jose CA
Herman M. Chang - Cupertino CA
Bai Nguyen - San Jose CA
Giap H. Tran - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 738

US Classification:

326 38, 326 41

Abstract:

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBEs) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBEs) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBEs may be synthetically combined to efficiently define 4:1 DyMUXs with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBBs may be synthetically combined to efficiently define 8:1 DyMUXs with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg.

US Patent:

6621298, Sep 16, 2003

Filed:

Mar 4, 2002

Appl. No.:

10/090209

Inventors:

Om P. Agrawal - Los Altos CA
Herman M. Chang - Cupertino CA
Bradley A. Sharpe-Geisler - San Jose CA
Giap H. Tran - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19094

US Classification:

326 50, 326113

Abstract:

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGBs) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUTs) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUTs and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section.

US Patent:

RE39510, Mar 13, 2007

Filed:

Mar 20, 2003

Appl. No.:

10/392751

Inventors:

Om P. Agrawal - Los Altos CA, US
Herman M. Chang - Cupertino CA, US
Bradley A. Sharpe-Geisler - San Jose CA, US
Bai Nguyen - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 7/38
H03K 19/177

US Classification:

326 40, 326 38

Abstract:

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.

US Patent:

6163168, Dec 19, 2000

Filed:

Dec 9, 1998

Appl. No.:

9/208203

Inventors:

Bai Nguyen - San Jose CA
Om P. Agrawal - Los Altos CA
Bradley A. Sharpe-Geisler - San Jose CA
Jack T. Wong - Fremont CA
Herman M. Chang - Cupertino CA

Assignee:

Vantis Corporation - Sunnyvale CA

International Classification:

H01L 2500
H03K 19177

US Classification:

326 41

Abstract:

A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.

US Patent:

62929305, Sep 18, 2001

Filed:

Jun 22, 2000

Appl. No.:

9/603119

Inventors:

Om P. Agrawal - Los Altos CA
Bradley A. Sharpe-Geisler - San Jose CA
Herman M. Chang - Cupertino CA
Giap H. Tran - San Jose CA

Assignee:

Vantis Corporation - Sunnyvale CA

International Classification:

G06F 1750
H03K 19173
H03K 19177

US Classification:

716 16

Abstract:

A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.

US Patent:

60972122, Aug 1, 2000

Filed:

Oct 9, 1997

Appl. No.:

8/948306

Inventors:

Om P. Agrawal - Los Altos CA
Herman M. Chang - Cupertino CA
Bradley A. Sharpe-Geisler - San Jose CA
Giap H. Tran - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Sunnyvale CA

International Classification:

H03K 19177
H01L 2500

US Classification:

326 41

Abstract:

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions.