Hien T Le

US Patent:

7716546, May 11, 2010

Filed:

Oct 3, 2007

Appl. No.:

11/866787

Inventors:

Hien Minh Le - Cedar Park TX, US
Robert Christopher Dixon - Austin TX, US
Luis Carlos Medina - Lago Vista TX, US
Tung Nguyen Pham - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714729, 714733, 714739, 714 25

Abstract:

A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.

US Patent:

8296520, Oct 23, 2012

Filed:

Dec 19, 2007

Appl. No.:

11/959652

Inventors:

Hien Minh Le - Cedar Park TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711124, 711121, 711135, 711143

Abstract:

A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response.

US Patent:

8397029, Mar 12, 2013

Filed:

Dec 19, 2007

Appl. No.:

11/959793

Inventors:

Richard Nicholas - Round Rock TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Hien Minh Le - Cedar Park TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711118, 711119, 711122, 711124, 711144, 711145, 711146, 711154

Abstract:

A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

US Patent:

20200301838, Sep 24, 2020

Filed:

May 28, 2019

Appl. No.:

16/424452

Inventors:

- Suwon-si, KR
Hien LE - Cedar Park TX, US
Tarun NAKRA - Austin TX, US
Yingying TIAN - Austin TX, US
Apurva PATEL - Austin TX, US
Omar TORRES - Austin TX, US

International Classification:

G06F 12/0831
G06F 12/0868
G06F 11/07

Abstract:

According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

US Patent:

20190266093, Aug 29, 2019

Filed:

May 13, 2019

Appl. No.:

16/410279

Inventors:

- Armonk NY, US
Hien M. Le - Cedar Park TX, US
Hugh Shen - Round Rock TX, US
Derek E. Williams - Austin TX, US
Phillip G. Williams - Leander TX, US

International Classification:

G06F 12/0831
G06F 12/0862

Abstract:

Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

US Patent:

20180052771, Feb 22, 2018

Filed:

Oct 27, 2017

Appl. No.:

15/796507

Inventors:

- Armonk NY, US
Hien M. Le - Cedar Park TX, US
Hugh Shen - Round Rock TX, US
Derek E. Williams - Austin TX, US
Phillip G. Williams - Leander TX, US

International Classification:

G06F 12/0831
G06F 12/0862

Abstract:

Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

US Patent:

20160062891, Mar 3, 2016

Filed:

Aug 29, 2014

Appl. No.:

14/473687

Inventors:

- ARMONK NY, US
HIEN M. LE - CEDAR PARK TX, US
WILLIAM J. STARKE - ROUND ROCK TX, US
DEREK E. WILLIAMS - AUSTIN TX, US
PHILLIP G. WILLIAMS - LEANDER TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 12/08
G06F 9/46

Abstract:

In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line.

US Patent:

20160062892, Mar 3, 2016

Filed:

Oct 24, 2014

Appl. No.:

14/523229

Inventors:

- ARMONK NY, US
HIEN M. LE - CEDAR PARK TX, US
WILLIAM J. STARKE - ROUND ROCK TX, US
DEREK E. WILLIAMS - AUSTIN TX, US
PHILLIP G. WILLIAMS - LEANDER TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 12/08
G06F 12/12

Abstract:

In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line.