Hiral Ajmera - Sunnyvale CA, US Roman Mostovoy - San Francisco CA, US Glen Mori - Pacifica CA, US
Assignee:
Applied Materials, Inc.
International Classification:
C25D005/34
US Classification:
205/099000, 205/101000
Abstract:
Embodiments of the invention provide a method for removing contaminants from a plating bath contained in a weir-type plater during idle times. The method broadly includes positioning a lower portion of a substrate support assembly into the plating bath and rotating the substrate support assembly at a rotation rate of between about 1 rpm and about 60 rpm for between about 5 seconds and about 30 seconds to circulate the plating solution such that contaminants accumulating on the surface of the plating solution are urged to flow over a weir of the weir-type plater.
Rajeev Bajaj - Fremont CA, US Ramin Emami - San Jose CA, US Girish Dixit - San Jose CA, US Hiral Ajmera - Sunnyvale CA, US Roman Mostovoy - San Francisco CA, US
Assignee:
Applied Materials, Inc.
International Classification:
C25D021/06 C25D021/16 C25D017/00
US Classification:
205/098000, 204/276000, 205/099000
Abstract:
A method and apparatus for removing degraded organics from an electroplating solution by passing at least a portion of electroplating solution through a filter. The apparatus generally includes a deposition cell including a fluid inlet, a fluid reservoir, and at least one filter disposed between the reservoir and the fluid inlet. The apparatus may further include a control valve disposed between the fluid reservoir and the fluid inlet for passing at least a portion of an electroplating solution to a recovery stream including the at least one filter. Embodiments of the invention further include a method generally including the steps of providing a substrate having a seed layer disposed on a surface thereof, disposing the substrate in an electroplating solution, flowing a portion of the electroplating solution through a filter in an amount sufficient to remove an amount of organic additives from the electroplating solution equal to a calculated rate of organic additive degradation, and flowing the electroplating solution to the substrate.
Intel Corporation 2007 - 2013
Senior Process Integration Engineer, Beol
Intel Corporation 2007 - 2013
Platform Lead and Manager, Assembly Test Technology Development
Applied Materials Feb 2001 - Jan 2003
Process Engineer Ii
Feb 2001 - Jan 2003
Platform Lead and Manager, Assembly Test
Education:
University of Florida 2003 - 2007
Doctorates, Doctor of Philosophy, Chemical Engineering
Rensselaer Polytechnic Institute 1999 - 2001
Master of Science, Masters, Chemical Engineering
Maharaja Sayarirao University 1995 - 1999
Bachelor of Engineering, Bachelors, Chemical Engineering
Skills:
Development Pecvd Dry Etch Wet Chemical Etching Technology Photolithography Platform Ecp Chemical Engineering Immersion Lithography Tem Jmp Thin Films Atomic Layer Deposition Characterization Metallization Process Integration Process Simulation Processes Development Beol Semiconductor Industry Design of Experiments Ald Cvd Failure Analysis Lithography Semiconductors Spc Process Engineering Afm Metrology R&D Silicon Doe Materials Science
National University of Singapore 2019 - 2020
Master of Business Administration, Masters
University of Florida 2003 - 2007
Doctorates, Doctor of Philosophy
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