Ho-Ming Leung - Cupertino CA, US Fan Zhang - San Jose CA, US Kasturiranga N. Rangam - Santa Clara CA, US Venkatesh Balasubramanian - Santa Clara CA, US
An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.
Context Based Adaptive Binary Arithmetic Codec Architecture For High Quality Video Compression And Decompression
Elliot N. Linzer - Suffern NY, US Ho-Ming Leung - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03M007/00
US Classification:
341107
Abstract:
A method for compressing/decompressing data, comprising the steps of translating a first representation of data to a second representation of the data and translating the second representation of the data to a third representation of the data.
2-D Luma And Chroma Dma Optimized For 4 Memory Banks
Elliot N. Linzer - Suffern NY, US Ho-Ming Leung - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 13/00 G06F 12/02
US Classification:
345537, 345543, 345544
Abstract:
A method for storing data of a plurality of components of an image in a memory system with four banks comprising the steps of (A) placing a first portion of data of a first component of the plurality of components into a first bank of the four banks and (B) placing a second portion of the data of the first component in a second bank of the four banks, where all of the data of the first component is stored in the first and second banks and occupies at least three pages in the memory system.
Ho-Ming Leung - Cupertino CA, US Fan Zhang - San Jose CA, US Gary Chang - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 11/00
US Classification:
714 30, 714733
Abstract:
An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.
Elliot N. Linzer - Suffern NY, US Ho-Ming Leung - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 13/00 G06F 13/28 G09G 5/399 G09G 5/36
US Classification:
345536, 345540, 345533, 345547
Abstract:
An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.
Memory Video Data Storage Structure Optimized For Small 2-D Data Transfer
Elliot N. Linzer - Suffern NY, US Ho-Ming Leung - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 9/64 G11C 8/00
US Classification:
348716, 345547, 36523004
Abstract:
An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.
Integrated Clock Generator With Programmable Spread Spectrum Using Standard Pll Circuitry
Ho-Ming Leung - Cupertino CA, US Elliot Sowadsky - San Jose CA, US Eric Hung - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03L 7/06
US Classification:
327147, 327156
Abstract:
An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.
Real Time Clock Architecture And/Or Method For A System On A Chip (Soc) Application
Ho-Ming Leung - Cupertino CA, US Remi C. Lenoir - Menlo Park CA, US Zoltan Toth - Sunnyvale CA, US Daniel S. Perrin - Fresno CA, US Eric Hung - San Jose CA, US Timothy J. Wilson - Oldham, GB
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1/04
US Classification:
713502, 713500, 713600, 365229
Abstract:
An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.
Marseille 2013 - 2014
Engineer
Entropic Communications 2013 - 2014
Principal Vlsi Engineer of Home Network Products
Lsi Corporation Aug 1998 - Dec 2006
Architect of Set-Top Box and Dvd Recorder
C-Cube Microsystems 1998 - 2001
Design Engineer
Cypress Semiconductor Corporation Jan 1988 - Jan 1992
Staff Engineer
Education:
University of California, Berkeley 1983 - 1984
Masters, Master of Science In Electrical Engineering
University of Pennsylvania 1980 - 1983
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Asic Verilog Vlsi Ic Soc Semiconductors Embedded Systems C Fpga Integrated Circuit Design Digital Signal Processors Algorithms Rtl Design Architecture Systemc Static Timing Analysis Systemverilog Functional Verification Eda Tcl Set Top Box