Hoang Tran

US Patent:

58215832, Oct 13, 1998

Filed:

Mar 6, 1996

Appl. No.:

8/610563

Inventors:

Fwu-Iuan Hshieh - Saratoga CA
Lih-Ying Ching - Cupertino CA
Hoang Tran - San Jose CA
Mike F. Chang - Cupertino CA

Assignee:

Siliconix incorporated - Santa Clara CA

International Classification:

H01L 2978

US Classification:

257330

Abstract:

A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i. e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region at the bottom of the trench and in the upper portion of the drift region. This N JFET region (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.