Hongjiang S Song

US Patent:

6466615, Oct 15, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/475486

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 740

US Classification:

375232, 375350, 708313, 708316, 708322, 341141, 341142, 341159

Abstract:

An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

US Patent:

6469646, Oct 22, 2002

Filed:

May 29, 2001

Appl. No.:

09/867155

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 166

US Classification:

341144, 341145, 341154

Abstract:

A way of converting digital signals to analog signals is provided. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.

US Patent:

6531896, Mar 11, 2003

Filed:

Dec 28, 1999

Appl. No.:

09/473738

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190175

US Classification:

326 86

Abstract:

A method includes selecting either a current signaling mode or a voltage signaling mode to communicate with a serial bus. When the current signaling mode is selected, an output stage is placed in the current signaling mode, and when the voltage signaling mode is selected, the output stage is placed in the voltage signaling mode.

US Patent:

6570931, May 27, 2003

Filed:

Dec 31, 1999

Appl. No.:

09/476634

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 2704

US Classification:

375295, 327108, 327261, 327276

Abstract:

An apparatus including a switched voltage bit cell (SVBC) array to receive an input voltage signal, each bit cell of the SVBC array configured to add a voltage to the input voltage signal and a delay locked-loop configured to delay an output voltage signal of each bit cell of the SVBC array by a determined step.

US Patent:

6633248, Oct 14, 2003

Filed:

Aug 23, 2002

Appl. No.:

10/226945

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 166

US Classification:

341144, 341145, 341154

Abstract:

A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.

US Patent:

6639956, Oct 28, 2003

Filed:

Dec 31, 1999

Appl. No.:

09/476978

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 700

US Classification:

375354, 375375, 375372, 327158, 710 61, 713401

Abstract:

An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.

US Patent:

6775345, Aug 10, 2004

Filed:

Dec 30, 1999

Appl. No.:

09/475497

Inventors:

Hongjiang Song - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03D 324

US Classification:

375376, 709400

Abstract:

An apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay the sampled data by the detected phase difference.

US Patent:

6838945, Jan 4, 2005

Filed:

Aug 19, 2003

Appl. No.:

10/644203

Inventors:

Hongjiang Song - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 700

US Classification:

331 1A, 375376, 327156

Abstract:

An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.