Hongqiang Qiang Lu

US Patent:

6777807, Aug 17, 2004

Filed:

May 29, 2003

Appl. No.:

10/448082

Inventors:

Valeriy Sukharev - Cupertino CA
Wilbur G. Catabay - Saratoga CA
Hongqiang Lu - Gresham OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348

US Classification:

257751, 257750, 257758, 257763, 257764, 257785

Abstract:

A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

US Patent:

6884720, Apr 26, 2005

Filed:

Aug 25, 2003

Appl. No.:

10/648602

Inventors:

Hongqiang Lu - Lake Oswego OR, US
Wilbur G. Catabay - Saratoga CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L021/44

US Classification:

438687, 438249

Abstract:

A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

US Patent:

6969651, Nov 29, 2005

Filed:

Mar 26, 2004

Appl. No.:

10/810760

Inventors:

Hongqiang Lu - Lake Oswego OR, US
William Barth - Gresham OR, US
Peter A. Burke - Portland OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L021/336

US Classification:

438257, 438592, 438690, 365151

Abstract:

Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.

US Patent:

6987059, Jan 17, 2006

Filed:

Aug 14, 2003

Appl. No.:

10/641768

Inventors:

Peter A. Burke - Portland OR, US
Hongqiang Lu - Lake Oswego OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438627, 438643, 438687

Abstract:

A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

US Patent:

7033929, Apr 25, 2006

Filed:

Dec 23, 2002

Appl. No.:

10/328333

Inventors:

Peter A. Burke - Portland OR, US
William K. Barth - Gresham OR, US
Hongqiang Lu - Fremont CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438638, 438618, 438672, 438640

Abstract:

A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

US Patent:

7196420, Mar 27, 2007

Filed:

Oct 26, 2005

Appl. No.:

11/259965

Inventors:

Peter A. Burke - Portland OR, US
Hongqiang Lu - Lake Oswego OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 23/48

US Classification:

257751, 257734, 257767

Abstract:

A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

US Patent:

7312532, Dec 25, 2007

Filed:

Mar 24, 2005

Appl. No.:

11/090107

Inventors:

Peter A. Burke - Portland OR, US
William K. Barth - Gresham OR, US
Hongqiang Lu - Fremont CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/52
H01L 23/48

US Classification:

257774, 257776

Abstract:

A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

US Patent:

7675177, Mar 9, 2010

Filed:

Mar 7, 2005

Appl. No.:

11/074456

Inventors:

Hongqiang Lu - Lake Oswego OR, US
Wilbur G. Catabay - Saratoga CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257774, 257E21575, 257E21627, 257E21641

Abstract:

A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.