Hui Zhang Sun

US Patent:

8201207, Jun 12, 2012

Filed:

Dec 15, 2008

Appl. No.:

12/334777

Inventors:

James S. An - Sunnyvale CA, US
Hui Sun - San Jose CA, US
De Fu Li - Wayland MA, US
Keil Brewer - San Jose CA, US
John J. Downey - Apex NC, US
Chrisanto D. Leano - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04N 7/173

US Classification:

725111, 370225, 370252, 370397, 370399, 375219, 375222, 709223, 709224

Abstract:

Disclosed are apparatus and methods for managing upstream channels on a per cable modem basis. In certain embodiments, one or more thresholds are defined for each of a plurality of upstream logical channels of a headend system for receiving data from a plurality of cable modems (or other types of access nodes). Each defined threshold corresponds to a measurable parameter of the corresponding upstream logical channel. One or more metrics are collected for each cable modem of each upstream logical channel. It is determined whether to downgrade a selected cable modem to a selected one of the logical channels that has a lower performance level than the selected cable modem's current logical channel. Such downgrade determination is based on whether the selected cable modem's collected one or more metrics have failed a condition of the one or more defined thresholds and whether a percentage of a total of the cable modems of such current logical channel that have failed a condition for the one or more defined thresholds is less than a predefined percentage level. The selected cable modem is then caused to move from the current logical channel to the selected logical channel when the percentage of the total cable modems that have failed is below a predefined level if such selected logical channel is available.

US Patent:

8310926, Nov 13, 2012

Filed:

Feb 18, 2010

Appl. No.:

12/708313

Inventors:

Alon S. Bernstein - Sunnyvale CA, US
Gitesh Shah - San Jose CA, US
Cindy Chan - San Jose CA, US
Hui Sun - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G08C 15/00

US Classification:

370230, 370437, 370468

Abstract:

Load balancing across RF channels in a cable plant is challenging where individual cable modems have multiple receive/transmit channels. Load balancing may be taken into account in the assignments of channels to requesting modems in a registration process. Requesting modems may be registered in a sequence of descending order defined by the number of channels requested. Channel sets may be selected to minimize a maximum delta metric of load balancing. It is preferred to normalize the “weight” of a modem on a channel based on the modem capabilities. The relative weight may be inversely related to the number of channels supported by the modem. Load balancing techniques disclosed may be applied to both upstream and downstream channels. Current load balance quality is estimated and reported to an operator.

US Patent:

20220336223, Oct 20, 2022

Filed:

Jun 22, 2022

Appl. No.:

17/846155

Inventors:

- Santa Clara CA, US
Xuesong Lu - San Jose CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Andrew Nguyen - San Jose CA, US
Philip A. Kraus - San Jose CA, US
Chung Nang Liu - Foster City CA, US
Hui Sun - San Jose CA, US
Yufei Hu - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311
H01L 21/02
H01J 37/32
H01L 21/683
H01L 21/3105
H01L 21/67
H01L 21/8234

Abstract:

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

US Patent:

20210366722, Nov 25, 2021

Filed:

May 22, 2020

Appl. No.:

16/881145

Inventors:

- Santa Clara CA, US
Xuesong Lu - San Jose CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Andrew Nguyen - San Jose CA, US
Philip A. Kraus - San Jose CA, US
Chung Nang Liu - Foster City CA, US
Hui Sun - San Jose CA, US
Yufei Hu - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311
H01L 21/02
H01J 37/32
H01L 21/683
H01L 21/3105
H01L 21/67
H01L 21/8234

Abstract:

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

US Patent:

20190043723, Feb 7, 2019

Filed:

Jul 16, 2018

Appl. No.:

16/035994

Inventors:

- Santa Clara CA, US
Yangchung LEE - Oakland CA, US
Chain LEE - Sunnyvale CA, US
Hui SUN - Santa Clara CA, US
Jonathan Sungehul KIM - Danville CA, US

International Classification:

H01L 21/033
H01L 21/3213
H01L 21/311

Abstract:

Implementations described herein generally relate to an etching process for etching materials with high selectivity. In one implementation, a method of etching a gate material to form features in the gate material is provided. The method includes (a) exposing a cobalt mask layer to a fluorine-containing gas mixture in a first mode to form a passivation film on the cobalt mask layer. The cobalt mask layer exposes a portion of a gate material disposed on a substrate. The method further comprises (b) exposing the portion of the gate material to an etching gas mixture in a second mode to etch the portion of the gate material. The portion of the gate material is etched through openings defined in the cobalt mask layer and the portion of the gate material is etched at a greater rate than the cobalt mask layer having the passivation layer disposed thereon.

US Patent:

20160293420, Oct 6, 2016

Filed:

Feb 12, 2016

Appl. No.:

15/043183

Inventors:

- Santa Clara CA, US
Hui SUN - Santa Clara CA, US
Chung LIU - Foster City CA, US
Benjamin SCHWARZ - San Jose CA, US

International Classification:

H01L 21/033
H01L 21/32
H01L 21/311

Abstract:

Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.