Hui B Zheng

US Patent:

6944006, Sep 13, 2005

Filed:

Apr 3, 2003

Appl. No.:

10/406889

Inventors:

Hui Zheng - San Jose CA, US
Kenneth Tsai - Redwood City CA, US
Hong Wang - Cupertino CA, US
Yongxiang He - Sunnyvale CA, US
Daniel M. Deyo - Cedar Park TX, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01T023/00

US Classification:

361234

Abstract:

A guard for an electrostatic chuck includes a ceramic annulus that has an inner surface shaped to fit around a circumference of the electrostatic chuck, and an outer surface having (i) a top portion with a recessed trench and (ii) a side portion. A metal coating is provided on the top portion of the outer surface.

US Patent:

8473876, Jun 25, 2013

Filed:

Jul 20, 2007

Appl. No.:

11/781054

Inventors:

Emre Tuncer - Santa Cruz CA, US
Hui Zheng - Round Rock TX, US
Vivek Raghavan - Mountain View CA, US
Anirudh Devgan - Austin TX, US
Amir Ajami - Sunnyvale CA, US
Alessandra Nardi - Hayward CA, US
Tao Lin - Sunnyvale CA, US
Pramod Thazhathethil - Bangalore, IN
Alfred Wong - Brookline MA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 54, 716 51, 716 55, 716113

Abstract:

A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

US Patent:

8572523, Oct 29, 2013

Filed:

Jul 20, 2007

Appl. No.:

11/781043

Inventors:

Emre Tuncer - Santa Cruz CA, US
Hui Zheng - Round Rock TX, US
Vivek Raghavan - Mountain View CA, US
Anirudh Devgan - Austin TX, US
Amir Ajami - Sunnyvale CA, US
Alessandra Nardi - Hayward CA, US
Tao Lin - Sunnyvale CA, US
Pramod Thazhathethil - Bangalore, IN
Alfred Wong - Brookline MA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 55, 716 52, 716 53, 716 54, 716112, 716113, 716133, 716134, 716136, 703 16

Abstract:

A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.