Hung M Le

US Patent:

6356918, Mar 12, 2002

Filed:

Jul 26, 1995

Appl. No.:

08/507542

Inventors:

Chiao-Mei Chuang - Cupertino CA
Hung Qui Le - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

707203, 707202, 712 34, 712218, 712219, 712228, 712230, 712233, 712234, 712236

Abstract:

A method and a system in a data processing system for managing registers in a register array wherein the data processing system has M architected registers and the register array has greater than M registers. A first physical register address is selected from a group of available physical register addresses in a renamed table in response to dispatching a register-modifying instruction that specifies an architected target register address. The architected target register address is then associated with the first physical register address, and a result of executing the register-modifying instruction is stored in a physical register pointed to by the first physical register address. In response to completing the register-modifying instruction, the first physical address in the rename table is exchanged with a second physical address in a completion renamed table, wherein the second physical address is located in the completion rename table at a location pointed to by the architected target register address. Therefore, upon instruction completion, the completion rename table contains pointers that map architected register addresses to physical register addresses. The rename table maps architected register addresses to physical register addresses for instructions currently being executed, or for instructions that have âfinishedâ and have not yet been âcompleted.

US Patent:

6424510, Jul 23, 2002

Filed:

Apr 28, 2000

Appl. No.:

09/560632

Inventors:

Janardhanan S. Ajit - Sunnyvale CA
Hung Pham Le - San Jose CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H02H 900

US Classification:

361 59, 361 911, 361111, 361127

Abstract:

The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source. The second voltage divider has a node connected to a gate of the second NMOS transistor.

US Patent:

6452248, Sep 17, 2002

Filed:

Aug 14, 2000

Appl. No.:

09/639707

Inventors:

Hung Pham Le - San Jose CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H01L 2900

US Classification:

257530, 438131

Abstract:

A programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby programming the MOS transistor. A programming circuit with the MOS transistor in a feedback path is provided. This feedback provides a self-timing feature, such that immediately after the fuse is programmed, its programming operation ceases.

US Patent:

6501320, Dec 31, 2002

Filed:

Jul 25, 2000

Appl. No.:

09/625237

Inventors:

Hung Pham Le - San Jose CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03K 508

US Classification:

327330, 327 55, 327 57

Abstract:

A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier circuit, respectively. The invention provides a self-contained, self-powered, self-regulated low turn-on voltage diode-rectifier with maximum current (on-state conductance) when forward-biased. This circuit can be inserted between any two nodes and behaves like a Schottky diode.

US Patent:

7012794, Mar 14, 2006

Filed:

Jan 17, 2003

Appl. No.:

10/346964

Inventors:

Hung Pham Le - San Jose CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

H02H 9/00

US Classification:

361 911, 361 56

Abstract:

An analog transfer gate that can be connected to an external line of a chip that is also connected to a digital circuit. The transfer gate includes both NMOS and PMOS transistors for passing the analog signals in both directions. A voltage sensing circuit is connected to the external line and is configured to sense a voltage that is higher than the supply voltage of the analog circuit. When this occurs, it produces a sense output signal. The sense output signal activates a protection enabling circuit that turns off the PMOS and NMOS transistors. In addition, at least one additional protection transistor is activated to avoid too high of a voltage being applied across any of the transistor junctions.

US Patent:

7481835, Jan 27, 2009

Filed:

Oct 29, 2004

Appl. No.:

10/976550

Inventors:

Stephen Dirk Pacetti - San Jose CA, US
Hung Manh Le - San Jose CA, US
Anthony Andreacchi - San Jose CA, US
Manish Gada - Santa Clara CA, US

Assignee:

Advanced Cardiovascular Systems, Inc. - Santa Clara CA

International Classification:

A61F 2/06

US Classification:

623 115, 623901

Abstract:

This disclosure provides a description of medical devices with polymeric cobwebbing disposed near the surfaces of the medical device. This cobwebbing can contain drug(s) and can enhance the mechanical and chemical function of intraluminal stents. Methods of using these devices and methods of preparing the devices are disclosed, as well.

US Patent:

7683696, Mar 23, 2010

Filed:

Dec 26, 2007

Appl. No.:

11/964467

Inventors:

Hung Pham Le - San Jose CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

G05F 1/10

US Classification:

327534, 327535

Abstract:

An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells.

US Patent:

7704544, Apr 27, 2010

Filed:

Oct 7, 2003

Appl. No.:

10/680905

Inventors:

Stephen D. Pacetti - San Jose CA, US
Hung Manh Le - San Jose CA, US

Assignee:

Advanced Cardiovascular Systems, Inc. - Santa Clara CA

International Classification:

B05D 1/00

US Classification:

427 224, 427 225, 42742801, 42742802

Abstract:

A system and method for coating a tubular implantable medical device, such as a stent, using an applicator and a coating composition are provided.

Address:

3213 Knights Brg Rd, San Jose, CA 95132

Phone:

(408)7290521

VIN:

WBAWB73547P155430

Make:

BMW

Model:

3 SERIES

Year:

2007