Hung K Le

Address:

8200 Broadway St #808, Houston, TX 77061

Phone:

(713)6498045

VIN:

3TMJU4GNXAM101644

Make:

TOYOTA

Model:

TACOMA

Year:

2010

Address:

12011 New Brunswick Dr, Houston, TX 77089

Phone:

(281)4816171

VIN:

1HGCP36768A076635

Make:

HONDA

Model:

ACCORD

Year:

2008

Address:

1423 Gregg St, Houston, TX 77020

VIN:

5TETX22N78Z515747

Make:

TOYOTA

Model:

TACOMA

Year:

2008

Address:

513 Golden Bear Dr, Austin, TX 78738

Phone:

(512)4029116

VIN:

JTMZK33V276006559

Make:

TOYOTA

Model:

RAV4

Year:

2007

Address:

10526 Linsley Ln, Houston, TX 77034

Phone:

(832)2791158

VIN:

5TFRT54187X014079

Make:

TOYOTA

Model:

TUNDRA

Year:

2007

Address:

9227 Dawnfields Dr, Houston, TX 77064

VIN:

2HGFG12627H540311

Make:

HONDA

Model:

CIVIC

Year:

2007

Address:

2202 Munger St, Houston, TX 77023

VIN:

2T1KR32E07C649502

Make:

TOYOTA

Model:

MATRIX

Year:

2007

US Patent:

6336183, Jan 1, 2002

Filed:

Feb 26, 1999

Appl. No.:

09/259140

Inventors:

Hung Qui Le - Austin TX
Robert Greg McDonald - Austin TX
David James Shippy - Austin TX
Larry Edward Thatcher - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9312

US Classification:

712225, 712208, 712221, 712222

Abstract:

In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

US Patent:

6345356, Feb 5, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354498

Inventors:

John Edward Derrick - Round Rock TX
Lee Evan Eisen - Austin TX
Hung Qui Le - Austin TX
Robert Greg McDonald - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9312

US Classification:

712216, 712217, 712225

Abstract:

A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No OperationâInternal Operations (NOPâIOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.

US Patent:

6356918, Mar 12, 2002

Filed:

Jul 26, 1995

Appl. No.:

08/507542

Inventors:

Chiao-Mei Chuang - Cupertino CA
Hung Qui Le - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

707203, 707202, 712 34, 712218, 712219, 712228, 712230, 712233, 712234, 712236

Abstract:

A method and a system in a data processing system for managing registers in a register array wherein the data processing system has M architected registers and the register array has greater than M registers. A first physical register address is selected from a group of available physical register addresses in a renamed table in response to dispatching a register-modifying instruction that specifies an architected target register address. The architected target register address is then associated with the first physical register address, and a result of executing the register-modifying instruction is stored in a physical register pointed to by the first physical register address. In response to completing the register-modifying instruction, the first physical address in the rename table is exchanged with a second physical address in a completion renamed table, wherein the second physical address is located in the completion rename table at a location pointed to by the architected target register address. Therefore, upon instruction completion, the completion rename table contains pointers that map architected register addresses to physical register addresses. The rename table maps architected register addresses to physical register addresses for instructions currently being executed, or for instructions that have âfinishedâ and have not yet been âcompleted.

US Patent:

6370649, Apr 9, 2002

Filed:

Mar 2, 1998

Appl. No.:

09/033192

Inventors:

Michael F. Angelo - Houston TX
David F. Heinrich - Tomball TX
Hung Q. Le - Katy TX
Richard O. Waldorf - Cypress TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

H04K 100

US Classification:

713202, 713100, 713200, 713182, 713183, 713184, 380249, 380 44, 235382, 2353825

Abstract:

A computer system according to the present invention implements a self-modifying âfail-safeâ password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.

US Patent:

6430678, Aug 6, 2002

Filed:

Jul 29, 1999

Appl. No.:

09/363463

Inventors:

James Allan Kahle - Austin TX
Hung Qui Le - Austin TX
Lee Evan Eisen - Austin TX
John Edward Derrick - Round Rock TX
Robert William Hay - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

712217, 712244

Abstract:

An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

US Patent:

6442675, Aug 27, 2002

Filed:

Jul 29, 1999

Appl. No.:

09/363464

Inventors:

John Edward Derrick - Round Rock TX
Lee Evan Eisen - Austin TX
Hung Qui Le - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

712209, 712211, 712225, 712241

Abstract:

A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.

US Patent:

6460139, Oct 1, 2002

Filed:

Nov 20, 1998

Appl. No.:

09/196549

Inventors:

David F. Heinrich - Tomball TX
Hung Q. Le - Katy TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

H04L 900

US Classification:

713200

Abstract:

A computer system, bus interface unit, and method is provided for programmably modifying securable resources of the computer. Those resources may be devices which can be coupled to peripheral buses of the computer, or which may contain or allow access to sensitive information that must be secured against improper access. The security system thereby functions to block accesses to certain devices based on the status of the user seeking access. Passwords stored in the security system are matched against locally and distally entered passwords from either the user of that particular computer system, an administrator of a subset of localized computer systems, or a system administrator in charge of all networked computer systems. The present security system is thereby hierarchical in nature and can be programmed by the system administrator such that the assignment of unlocked signals arising from password comparisons can be programmably mapped to various securable devices. In this fashion, a user can gain access to certain resources at one time and then later, based on the system administrator re-programming a slot assignment register, the user may no longer be given access to that device.

US Patent:

6463524, Oct 8, 2002

Filed:

Aug 26, 1999

Appl. No.:

09/383607

Inventors:

Maureen Delaney - Richmond VT
Hung Qui Le - Austin TX
Dung Quoc Nguyen - Austin TX
Robert McDonald - Austin TX
David W. Victor - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13364

US Classification:

712221, 712215

Abstract:

A superscalar processor and method are disclosed for efficiently executing a store instruction. The store instruction is stored in an issue queue within the processor. A first part of the store instruction is issued from the issue queue to a first one of different execution units in response to a first operand becoming available. A second part of the store instruction is issued from the issue queue to a second one of the different execution units in response to a second operand becoming available. The store instruction is completed in response to executing the first part of the store instruction by the first one of the execution units and the second part of the store instruction by the second one of the execution units.