Allen Hui-Wan Tseng - Mississauga, CA Hung Van Tang - San Jose CA Vinh Coung Ta - Pleasant Hill CA
Assignee:
Logic Express System, Inc. - Fremont CA
International Classification:
G06F9/455;13/00
US Classification:
395500
Abstract:
A hardware-based emulator is partitioned onto two boards. An emulation board has field-programmable gate array (FPGA) chips mounted on a top surface, and connection posts protruding through to the bottom surface. The I/O pins of the FPGA chips that carry emulated signals are connected to the connection posts but not directly to other FPGA chips on the emulation board. An interconnection board has a grid of wire-wrap posts. The tops of the wire wrap-posts mate with the connection posts when the emulation board is plugged in to the interconnection board. The wire-wrap posts extend through the interconnection board and out the bottom surface. Interconnection is made by wire-wrap wires wound around the wire-wrap posts. Thus interconnection between FPGA chips on the emulation board is made by wire-wrap on the interconnection board, while the logic gates are emulated in the FPGA chips on the separate emulation board. The interconnection can be changed by discarding the interconnection board and wrapping a new interconnection board, while using the same FPGA's on the emulation board.
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