Hyung J Kim

US Patent:

20130019216, Jan 17, 2013

Filed:

Mar 29, 2012

Appl. No.:

13/433909

Inventors:

Shobha Vasudevan - Champaign IL, US
David Sheridan - San Jose CA, US
Lingyi Liu - Champaign IL, US
Hyung Sul Kim - Urbana IL, US

Assignee:

The Board of Trustees of the University of Illinos - Urbana IL

International Classification:

G06F 17/50

US Classification:

716106

Abstract:

A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.