Ian England Young

US Patent:

6172937, Jan 9, 2001

Filed:

May 10, 1999

Appl. No.:

9/309049

Inventors:

Alper Ilkbahar - Santa Cruz CA
Simon M. Tam - Redwood City CA
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

365233

Abstract:

A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e. g. , phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.

Address:

1419 Antigua Ln, Houston, TX 77058

Phone:

(713)5217541

VIN:

1HGCM56857A112021

Make:

HONDA

Model:

ACCORD

Year:

2007