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Igor I Bol

Deceased

from Topanga, CA

Also known as:
  • Igor Izya Bol
  • Izya K Bol
Phone and address:
21110 Brunnell Ct, Topanga, CA 90290
(818)8846764

Igor Bol Phones & Addresses

  • 21110 Brunnell Ct, Topanga, CA 90290 • (818)8846764
  • 4616 Willis Ave, Sherman Oaks, CA 91403 • (818)9865258
  • 3718 Bobstone Dr, Sherman Oaks, CA 91423 • (818)9865258
  • 345 Potrero Ave, Sunnyvale, CA 94086
  • Los Angeles, CA

Work

  • Position:
    Professional/Technical
Name / Title
Company / Classification
Phones & Addresses
Igor I. Bol
Owner
Lollicut
Beauty Shop
18663 Ventura Blvd, Los Angeles, CA 91356
(818)3426171

Us Patents

  • Low Voltage Planar Power Mosfet With Serpentine Gate Pattern

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  • US Patent:
    6541820, Apr 1, 2003
  • Filed:
    Mar 28, 2000
  • Appl. No.:
    09/536903
  • Inventors:
    Igor Bol - Sherman Oaks CA
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 2976
  • US Classification:
    257341, 257342, 257343, 257344, 257355, 257365
  • Abstract:
    A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.
  • Mosfet With A Buried Gate

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  • US Patent:
    6570218, May 27, 2003
  • Filed:
    Jun 19, 2000
  • Appl. No.:
    09/593447
  • Inventors:
    Igor Bol - Sherman Oaks CA
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 2976
  • US Classification:
    257328, 257329, 257330
  • Abstract:
    An insulation is formed on a substrate of a material having a first conductivity type. A gate material is formed on the insulation. A portion of the gate material is removed thereby creating forming mesa type gate structures from remaining positions of the gate material. The mesas are then insulated. A channel forming layer, of a material having a second conductivity type, is formed between the produced mesas. Finally, a source of a material having the first conductivity type is formed on the channel forming layer.
  • Single Mask Trench Fred With Enlarged Schottky Area

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  • US Patent:
    6656843, Dec 2, 2003
  • Filed:
    Apr 25, 2002
  • Appl. No.:
    10/132551
  • Inventors:
    Igor Bol - Sherman Oaks CA
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 21302
  • US Classification:
    438694, 438700, 438723, 438724, 438743, 438744
  • Abstract:
    A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon and for subsequently etching trenches in the silicon. A boron implant is carried out in the bottoms of the trenches to form local P/N junctions. The oxide beneath the nitride is then fully stripped in the active area and only partly stripped in the termination area in which the trenches are wider spaced than in the active area. Aluminum is then deposited atop the active area and in the trenches, but is blocked from contact with silicon in the active area by the remaining nitride layer.
  • Manufacturing Process For Fast Recovery Diode

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  • US Patent:
    6699775, Mar 2, 2004
  • Filed:
    Aug 30, 2002
  • Appl. No.:
    10/234905
  • Inventors:
    Igor Bol - Sherman Oaks CA
    Iftikhar Ahmed - Bellflower CA
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 2128
  • US Classification:
    438514, 438524, 438531, 438570, 438571, 438580, 438482
  • Abstract:
    A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.
  • Method For Fabrication Of Mosfet With Buried Gate

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  • US Patent:
    6858499, Feb 22, 2005
  • Filed:
    Mar 31, 2003
  • Appl. No.:
    10/404989
  • Inventors:
    Igor Bol - Sherman Oaks CA, US
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L021/336
  • US Classification:
    438268, 257328
  • Abstract:
    An insulation is formed on a substrate of a material having a first conductivity type. A gate material is formed on the insulation. A portion of the gate material is removed thereby creating forming mesa type gate structures from remaining positions of the gate material. The mesas are then insulated. A channel forming layer, of a material having a second conductivity type, is formed between the produced mesas. Finally, a source of a material having the first conductivity type is formed on the channel forming layer.
  • High Density Fet With Self-Aligned Source Atop The Trench

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  • US Patent:
    7319059, Jan 15, 2008
  • Filed:
    Jan 31, 2005
  • Appl. No.:
    11/047243
  • Inventors:
    Igor Bol - Sherman Oaks CA, US
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 21/336
  • US Classification:
    438268, 438270, 438272
  • Abstract:
    A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implants to diffuse into the semiconductor region.
  • Dynamic Deep Depletion Field Effect Transistor

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  • US Patent:
    7462908, Dec 9, 2008
  • Filed:
    Jul 14, 2005
  • Appl. No.:
    11/181292
  • Inventors:
    Igor Bol - Sherman Oaks CA, US
    Xin Li - Torrance CA, US
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 29/76
  • US Classification:
    257328, 257330, 257331
  • Abstract:
    A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.
  • Double Sided Semiconduction Device With Edge Contact And Package Therefor

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  • US Patent:
    7944035, May 17, 2011
  • Filed:
    May 16, 2007
  • Appl. No.:
    11/803763
  • Inventors:
    Igor Bol - Sherman Oaks CA, US
  • Assignee:
    International Rectifier Corporation - El Segundo CA
  • International Classification:
    H01L 23/02
  • US Classification:
    257686, 257E23085, 257E23063, 257E23071, 257E29013, 257E29027, 257E29271, 257723, 257777, 257328, 257329, 257335, 257336, 257489, 257492, 257341, 257288, 257339, 257408, 257139, 257342, 257345, 257378, 257401, 257476, 257486
  • Abstract:
    A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of the die. Various packages for the die having a reduced foot print on a support substrate are disclosed.

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