Ilango S Ganga

US Patent:

7668194, Feb 23, 2010

Filed:

Dec 23, 2004

Appl. No.:

11/020945

Inventors:

Luke Chang - Aloha OR, US
Ilango S. Ganga - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04J 3/16
H04J 3/00

US Classification:

370465, 370474

Abstract:

A system and method to implement a dual speed network interface. A first code is transmitted from an initiator unit to a follower unit on a first output datapath (“OUT_DP”) of multiple OUT_DPs coupling the initiator unit to the follower unit. The first code is transmitted to initiate a speed change of a link to a physical medium for communicating data. The first code is transmitted at a first datapath speed. A second code is received on a first input datapath (“IN_DP”) of multiple IN_DPs coupling the follower unit to the initiator unit. The second code indicates to the initiator unit that the follower unit received the first code. The first OUT_DP is then placed into an idle state in response to receiving the second code. Subsequently, the first OUT_DP is enabled after the idle state at a second datapath speed different from the first datapath speed.

US Patent:

7676733, Mar 9, 2010

Filed:

Jan 4, 2006

Appl. No.:

11/325765

Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714775, 714776, 714789, 714821

Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

US Patent:

7720135, May 18, 2010

Filed:

Mar 15, 2004

Appl. No.:

10/801504

Inventors:

Bradley J. Booth - Austin TX, US
Luke Chang - Aloha OR, US
Ilango S. Ganga - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/38

US Classification:

375219, 370296, 370389, 370397, 370433, 710 58

Abstract:

Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

US Patent:

7873892, Jan 18, 2011

Filed:

Dec 16, 2009

Appl. No.:

12/639797

Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersberg, RU
Andrei Ovchinnikov - St. Petersberg, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714752, 714786, 714799, 714 4

Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

US Patent:

7885321, Feb 8, 2011

Filed:

Apr 1, 2010

Appl. No.:

12/752370

Inventors:

Bradley J. Booth - Austin TX, US
Luke Chang - Aloha OR, US
Ilango S. Ganga - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/38

US Classification:

375219, 370296, 370389, 370397, 370433, 710 58

Abstract:

Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

US Patent:

8108756, Jan 31, 2012

Filed:

Dec 9, 2010

Appl. No.:

12/964271

Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714775, 714789

Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

US Patent:

8307265, Nov 6, 2012

Filed:

Mar 9, 2009

Appl. No.:

12/381205

Inventors:

Ilango Ganga - Cupertino CA, US
Richard Mellitz - Prosperity SC, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714776, 714752, 370470, 370510, 370536

Abstract:

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802. 3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802. 3ap (2007).

US Patent:

8352828, Jan 8, 2013

Filed:

Jan 11, 2012

Appl. No.:

13/348341

Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714752, 714799

Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.