In Soon Kim

US Patent:

6346827, Feb 12, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/366937

Inventors:

Wayne Yeung - San Francisco CA
Chiakang Sung - Milpitas CA
Myron W. Wong - Fremont CA
Khai Nguyen - San Jose CA
Bonnie I. Wang - Cupertino CA
Xiaobao Wang - Santa Clara CA
Joseph Huang - San Jose CA
In Whan Kim - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 50, 326 45

Abstract:

A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

US Patent:

6630844, Oct 7, 2003

Filed:

Aug 22, 2001

Appl. No.:

09/887686

Inventors:

Yan Chong - Stanford CA
Chiakang Sung - Milpitas CA
Bonnie Wang - Cupertino CA
Khai Nguyen - San Jose CA
Joseph Huang - San Jose CA
Xiaobao Wang - Santa Clara CA
Philip Pan - Freemont CA
In Whan Kim - San Jose CA
Gopi Rangan - Santa Clara CA
Thomas H. White - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190175

US Classification:

326 82, 326 57

Abstract:

A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal; levels, including low supply signal levels, while limiting leakage current effects.

US Patent:

6661733, Dec 9, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/883087

Inventors:

Philip Y. Pan - Fremont CA
Chiakang Sung - Milpitas CA
Joseph Huang - San Jose CA
Bonnie Wang - Cupertino CA
Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
Gopinath Rangan - Santa Clara CA
In Whan Kim - San Jose CA
Yan Chong - Stanford CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523005, 365154

Abstract:

Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

US Patent:

6747903, Jun 8, 2004

Filed:

Jan 14, 2002

Appl. No.:

10/046939

Inventors:

Philip Y. Pan - Fremont CA
Chiakang Sung - Milpitas CA
Joseph Huang - San Jose CA
Bonnie Wang - Cupertino CA
Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
Gopinath Rangan - Santa Clara CA
In Whan Kim - San Jose CA
Yan Chong - Stanford CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

36518901, 36523005, 36523006, 36523002

Abstract:

Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.

US Patent:

6825692, Nov 30, 2004

Filed:

Jan 25, 2002

Appl. No.:

10/056367

Inventors:

Jonathan Chung - Newark CA
In Whan Kim - San Jose CA
Philip Pan - Freemont CA
Chiakang Sung - Milpitas CA
Bonnie Wang - Cupertino CA
Xiaobao Wang - Santa Clara CA
Yan Chong - Stanford CA
Gopinath Rangan - Santa Clara CA
Khai Nguyen - San Jose CA
Joseph Huang - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190175

US Classification:

326 68, 326 83, 327408

Abstract:

An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e. g. , programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

US Patent:

6870400, Mar 22, 2005

Filed:

Oct 3, 2003

Appl. No.:

10/678498

Inventors:

Yan Chong - Stanford CA, US
Chiakang Sung - Milpitas CA, US
Bonnie Wang - Cupertino CA, US
Khai Nguyen - San Jose CA, US
Joseph Huang - San Jose CA, US
Xiaobao Wang - Santa Clara CA, US
Philip Pan - Freemont CA, US
In Whan Kim - San Jose CA, US
Gopi Rangan - Santa Clara CA, US
Thomas H. White - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/0175

US Classification:

326 82, 326 57

Abstract:

A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

US Patent:

6992947, Jan 31, 2006

Filed:

Oct 28, 2003

Appl. No.:

10/696209

Inventors:

Philip Y. Pan - Fremont CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - San Jose CA, US
Bonnie Wang - Cupertino CA, US
Khai Nguyen - San Jose CA, US
Xiaobao Wang - Santa Clara CA, US
Gopinath Rangan - Santa Clara CA, US
In Whan Kim - San Jose CA, US
Yan Chong - Stanford CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523005, 365154

Abstract:

Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

US Patent:

7119579, Oct 10, 2006

Filed:

Dec 6, 2004

Appl. No.:

11/005890

Inventors:

Yan Chong - Stanford CA, US
Chiakang Sung - Milpitas CA, US
Bonnie Wang - Cupertino CA, US
Khai Nguyen - San Jose CA, US
Joseph Huang - San Jose CA, US
Xiaobao Wang - Santa Clara CA, US
Philip Pan - Freemont CA, US
In Whan Kim - San Jose CA, US
Gopi Rangan - Santa Clara CA, US
Thomas H. White - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 82, 326 38

Abstract:

A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.