Inhwan N Seo

US Patent:

7661078, Feb 9, 2010

Filed:

Feb 28, 2005

Appl. No.:

11/069759

Inventors:

David C. Noice - Palo Alto CA, US
William Kao - Fremont CA, US
Inhwan Seo - Fremont CA, US
Xiaopeng Dong - San Jose CA, US
Gary W. Nunn - Los Gatos CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 4, 716 5

Abstract:

Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.

US Patent:

8161425, Apr 17, 2012

Filed:

Apr 19, 2006

Appl. No.:

11/407873

Inventors:

David Noice - Palo Alto CA, US
Gary Nunn - Los Gatos CA, US
Inhwan Seo - Fremont CA, US
William Kao - Fremont CA, US
Xiaopeng Dong - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 55, 716 51, 716 52, 716 53, 716 54, 716 56, 430 5, 430 30

Abstract:

An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

US Patent:

7574685, Aug 11, 2009

Filed:

Apr 24, 2007

Appl. No.:

11/739622

Inventors:

Xiaopeng Dong - San Jose CA, US
Inhwan Seo - Fremont CA, US
William Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Gary Nunn - Los Gatos CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 11, 716 5

Abstract:

An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.