Jack B Lewis

US Patent:

20220317174, Oct 6, 2022

Filed:

Jun 8, 2022

Appl. No.:

17/835620

Inventors:

- Richardson TX, US
Jack Lewis - Richardson TX, US
Njteh Keleshian - Plano TX, US

International Classification:

G01R 31/28

Abstract:

A testing system for test sockets is presented having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A top stiffener is attached to the lower surface of the DUT PCB and is locked in place by engagement members of a locking mechanism, that is operated by an actuating mechanism, that includes a rack and pinion arrangement that converts rotational movement of the pinions to lateral movement of the racks thereby locking the stiffener connected to the DUT PCB to the socket plate so as to facilitate testing. The upper surface of the DUT PCB has an infinite top plane that is uninterrupted and can be of any size and shape. The system is also modular and can be formed of any number of modules depending on the pin count density required.

US Patent:

20220221489, Jul 14, 2022

Filed:

Apr 4, 2022

Appl. No.:

17/712392

Inventors:

- Richardson TX, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 1/073
G01R 31/28
G01R 1/04

Abstract:

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

US Patent:

20210041494, Feb 11, 2021

Filed:

Aug 3, 2020

Appl. No.:

16/983309

Inventors:

- Richardson TX, US
Jack Lewis - Richardson TX, US
Njteh Keleshian - Plano TX, US

International Classification:

G01R 31/28

Abstract:

A testing system for test sockets is presented having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A top stiffener is attached to the lower surface of the DUT PCB and is locked in place by engagement members of a locking mechanism, that is operated by an actuating mechanism, that includes a rack and pinion arrangement that converts rotational movement of the pinions to lateral movement of the racks thereby locking the stiffener connected to the DUT PCB to the socket plate so as to facilitate testing. The upper surface of the DUT PCB has an infinite top plane that is uninterrupted and can be of any size and shape. The system is also modular and can be formed of any number of modules depending on the pin count density required.

US Patent:

20200319231, Oct 8, 2020

Filed:

May 26, 2020

Appl. No.:

16/882917

Inventors:

- Cumming GA, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 1/073
G01R 31/28
G01R 1/04

Abstract:

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

US Patent:

20190072585, Mar 7, 2019

Filed:

Nov 6, 2018

Appl. No.:

16/181846

Inventors:

Lynwood Adams - Rockwall TX, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 1/073
G01R 1/04

Abstract:

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

US Patent:

20180120352, May 3, 2018

Filed:

Dec 22, 2017

Appl. No.:

15/852219

Inventors:

Lynwood Adams - Rockwall TX, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 1/073
G01R 1/04
G01R 31/28

Abstract:

A testing system for semiconductor chips having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. The DUT PCB is quickly and easily removed and replaced by moving the locking posts between an engaged position and a disengaged position. In this way, a single testing system can be used to test a great variety of semiconductor chips thereby reducing capital equipment costs and space needed in cleanrooms.

US Patent:

20170192046, Jul 6, 2017

Filed:

Mar 17, 2017

Appl. No.:

15/462383

Inventors:

- Rockwall TX, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 31/04

Abstract:

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

US Patent:

20160209443, Jul 21, 2016

Filed:

Jan 14, 2016

Appl. No.:

14/996045

Inventors:

- Rockwall TX, US
Jack Lewis - Royse City TX, US

International Classification:

G01R 1/04
G01R 31/26

Abstract:

A testing system for semiconductor chips having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. The DUT PCB is quickly and easily removed and replaced by moving the locking posts between an engaged position and a disengaged position. In this way, a single testing system can be used to test a great variety of semiconductor chips thereby reducing capital equipment costs and space needed in cleanrooms.