Jack E Weimer

US Patent:

6759842, Jul 6, 2004

Filed:

Apr 17, 2002

Appl. No.:

10/125725

Inventors:

Jack Edward Weimer - Grayslake IL

Assignee:

Eagle Test Systems, Inc. - Mundelein IL

International Classification:

G01R 104

US Classification:

3241581, 324754

Abstract:

A removable interface adapter includes a frame, a first set of contacts configured for connection to a first set of test head contacts in a test system, and a second set of contacts configured for connection to a test board having at least one device to be tested. The first and second adapter contacts are interconnected so that electronic devices placed in the test board can be tested by the test system. With this adapter, test boards made for one test system can be used on other test systems.

US Patent:

7561083, Jul 14, 2009

Filed:

Oct 31, 2007

Appl. No.:

11/933038

Inventors:

David Anderson - Gurnee IL, US
Jack Weimer - Grayslake IL, US

Assignee:

Eagle Test Systems, Inc. - Buffalo Grove IL

International Classification:

H03M 1/10

US Classification:

341120, 341155

Abstract:

Methods and apparatus, including computer program products, to test analog to digital converters, are disclosed. In general, data is received that characterizes a first digital code from a device under test at a first analog voltage of an analog signal generator and a second digital code being a digital code threshold, and a step size is generated for another test of the device by performing a calculation by a processor. The calculation may include multiplying a least significant bit size of the device with a difference of the first and second digital codes to generate a product, and dividing the product by a least significant bit size of the analog signal generator. The first digital code may be calculated from results from multiple subtests in the test, where each of the subtests includes multiple analog to digital conversions by the device at the first analog voltage.

US Patent:

20030135343, Jul 17, 2003

Filed:

Jan 15, 2002

Appl. No.:

10/047506

Inventors:

Gordon Samuelson - Lake Villa IL, US
Jack Weimer - Grayslake IL, US

Assignee:

EAGLE TEST SYSTEMS, INC.

International Classification:

G06F019/00
G01R027/28
G01R031/00
G01R031/14

US Classification:

702/117000

Abstract:

Apparatus for testing an electronic device under a plurality of test conditions created during a test sequence includes an arbitrary waveform generator that sequentially generates the plurality of test conditions. The test conditions include selectively forcing voltage or forcing current over a wide range of amplitudes, measuring a plurality of results with various resolutions and at selected times during the test sequence, changing filter settings, gains and other parameters. The test conditions are selected and set under the control of a system clock using data stored in memory. A controller initiates the test sequence of the apparatus and determines whether measured results are within predetermined specifications. The controller uses processor-driven software, but the settings of the test apparatus are changed at predetermined times during the test sequence, without controller intervention. Several test apparatus are typically managed by one controller. Performing test sequences without controller intervention reduces the time required for testing.

US Patent:

20200379043, Dec 3, 2020

Filed:

Jun 3, 2019

Appl. No.:

16/429668

Inventors:

- North Reading MA, US
Jack E. Weimer - Gurnee IL, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 31/319
G01R 31/28
G01R 31/317
G01R 31/3183
H03K 5/131
G01R 31/3167

Abstract:

Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.

US Patent:

20150276799, Oct 1, 2015

Filed:

Mar 26, 2014

Appl. No.:

14/225951

Inventors:

- North Reading MA, US
Jack E. Weimer - Gurnee IL, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 1/04
G01R 1/073
G01R 31/26

Abstract:

A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.

US Patent:

20150276803, Oct 1, 2015

Filed:

Mar 26, 2014

Appl. No.:

14/225918

Inventors:

- North Reading MA, US
Jack E. Weimer - Gurnee IL, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 1/04
G01R 1/073
G01R 31/26

Abstract:

A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.