Jacob Chen

US Patent:

20150228584, Aug 13, 2015

Filed:

Apr 21, 2014

Appl. No.:

14/257759

Inventors:

- Hsin-Chu, TW
Ming Xiang Li - San Jose CA, US
Edward Wan - Fremont CA, US
Jacob Chen - Los Altos CA, US
Dun-Nian Yaung - Hsin-Chu, TW
Cheng-Eng Daniel Chen - Richardson TX, US

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

H01L 23/538
H01L 25/065
H01L 25/00
H01L 21/768

Abstract:

An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.