Jae Woong Choi

US Patent:

20190043418, Feb 7, 2019

Filed:

May 9, 2018

Appl. No.:

15/975390

Inventors:

- Cupertino CA, US
Shyuan Yang - Burlingame CA, US
Tsung-Ting Tsai - Cupertino CA, US
Cheng-Ho Yu - Milpitas CA, US
Jae Won Choi - San Jose CA, US
Abbas Jamshidi Roudbari - San Jose CA, US
Ting-Kuo Chang - San Jose CA, US

International Classification:

G09G 3/3216
G09G 3/3283
G09G 3/3266
H01L 27/32

Abstract:

A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.

US Patent:

20140273357, Sep 18, 2014

Filed:

May 31, 2014

Appl. No.:

14/292868

Inventors:

- Milpitas CA, US
Jae Yong Choi - Pleasanton CA, US
Vladimir Tsukanov - Los Altos Hills CA, US

Assignee:

IXYS Corporation - Milpitas CA

International Classification:

H01L 29/66

US Classification:

438138, 438268

Abstract:

A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.