Jae W Park

US Patent:

6430187, Aug 6, 2002

Filed:

Jun 3, 1999

Appl. No.:

09/325185

Inventors:

Jae Park - Ossining NY

Assignee:

Fujitsu Network Communications, Inc. - Richardson TX

International Classification:

H04L 1256

US Classification:

370397, 370412, 370466, 370474

Abstract:

A network access device includes a cell buffer memory ( ) and segmentation and reassembly (SAR) logic ( ) between multiple local area network (LAN) interface logic blocks ( ) and logic ( ) interfacing with a cell-based network such as ATM. The cell buffer memory can be programmably partitioned into distinct buffer regions, each being associated with a respective LAN and with a respective set of virtual connections on the cell-based network. The SAR logic segments received frames into groups of cells, stores each group of cells into the buffer region associated with the respective LAN, and transfers the groups of cells from each buffer region to the cell-based-network interface logic via the associated virtual connections. The SAR logic and the cell memory are shared among multiple LAN bridges implemented by the LAN interface logic blocks and the cell-based-network interface logic, while traffic from the different bridges is kept separate. The SAR logic also manages the network bandwidth assigned to the different bridges separately, so that traffic from one bridge generally does not affect another bridges use of its allocated bandwidth.

US Patent:

6456962, Sep 24, 2002

Filed:

Jun 3, 1999

Appl. No.:

09/325186

Inventors:

Jon Allingham - New City NY
Bruce Pietsch - Orangeburg NY
Roy McNeil - Warwick NY
Jae Park - Ossining NY

Assignee:

Fujitsu Network Communications, Inc. - Richardson TX

International Classification:

G06F 1314

US Classification:

703 26, 703 27, 370387, 370395, 370401

Abstract:

LAN interface logic ( ) receives frames from a LAN segment ( ), and frame transport logic ( ) transfers frames to and from an ATM network. Forwarding logic ( ) is used to (i) determine whether a mapping between a destination address (DA) and a virtual connection (VC) in the ATM network exists, (ii) forward frames containing a known DA to the frame transport logic for transfer to the ATM network, (iii) forward frames containing unknown DAs to the frame transport logic for transfer to a broadcast and unknown server (BUS ) in the ATM network, and (iv) pass unknown DAs to a LAN emulation client (LEC) processor ( , FIG. ) to resolve the address. The LEC processor creates a LAN emulation address resolution protocol (LE_ARP) request message containing the unknown DA, and the LE_ARP request message is transferred to a LAN emulation server (LES ). The LES returns an ATM address of a remote LEC via which the destination node can be reached. The LEC processor uses the ATM address to establish a new VC to the destination node, and provides the DA-VC mapping to the forwarding logic for use in forwarding subsequently received frames.

US Patent:

6616394, Sep 9, 2003

Filed:

Dec 30, 1998

Appl. No.:

09/223111

Inventors:

Jae Heon Park - Cupertino CA

Assignee:

Silicon Valley Group - San Jose

International Classification:

B65H 500

US Classification:

41422201, 414217, 414937

Abstract:

Systems and methods are described for wafer processing. A wafer processing apparatus includes: a first wafer transporter; a process station coupled to the first wafer transporter, the process station including: a first plurality of wafer processing stacks, each of the plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to the plurality of wafer processing modules, each of the plurality of wafer processing modules adjacent, and accessible by, the second wafer transporter; and a third wafer transporter coupled to the process station, wherein any of the plurality of wafer processing modules in any of the plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters from among the first, second and third wafer transporter. The systems and methods provide advantages from minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization.

US Patent:

6646985, Nov 11, 2003

Filed:

Jun 3, 1999

Appl. No.:

09/325118

Inventors:

Jae Park - Ossining NY
Michael Samori - Nanuet NY

Assignee:

Fujitsu Network Communications, Inc. - Richardson TX

International Classification:

G01R 3108

US Classification:

370229, 370235, 370395, 709212, 709232

Abstract:

A congestion control mechanism in an ATM network access device includes segmentation and reassembly (SAR) logic that sends and receives Asynchronous Transfer Mode (ATM) cells to and from interface logic that transfers the cells to and from a switch fabric. The cells are transferred on ATM connections, including flow-controlled connections for which the sending of cells by the SAR logic is controlled in response to the settings of Generic Flow Control (GFC) bits appearing in the headers of ATM cells received by the SAR logic. The interface logic receives a congestion signal indicative of the level of congestion in a transmit buffer in the switch fabric. In response to the congestion signal, the interface logic sets the GFC bits in the headers of cells transferred to the SAR logic such that the cell transmission rate is maintained at a high average level while undesirable congestion in the transmit buffer is avoided. Hysteresis is employed in the setting of the GFC bits is response to the congestion signal. The interface logic generates idle cells during periods in which no traffic-carrying cells are being transferred from the switch fabric to the SAR logic, and sends the idle cells to the SAR logic to provide GFC signalling during such periods.

US Patent:

6746826, Jun 8, 2004

Filed:

Jul 25, 2000

Appl. No.:

09/624712

Inventors:

Jae Heon Park - Cupertino CA
Jung Suk Bang - Kyumggi-do, KR

Assignee:

ASML Holding N.V.

International Classification:

G03C 500

US Classification:

430322, 430325, 430331

Abstract:

Methods and apparatus are described for improved yield and line width performance for liquid polymers and other materials. A method for minimizing precipitation of developing reactant by lowering a sudden change in pH includes: developing at least a portion of a polymer layer on a substrate with an initial charge of a developer fluid; then rinsing the polymer with an additional charge of the developer fluid so as to controllably minimize a subsequent sudden change in pH; and then rinsing the polymer with a charge of another fluid. A method for achieving a more uniform, quasi-equilibrium succession of states from the introduction of developer chemical to the wafer surface to its removal is also described. The method reduces process-induced defects and improves critical dimension (CD) control.

US Patent:

6873690, Mar 29, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/255795

Inventors:

Eric E. Moon - Fort Lee NJ, US
Johng Phil Lee - Palisades Park NJ, US
Jae Heung Park - Fort Lee NJ, US
Taesoon Kim - Fort Lee NJ, US
Jong Phil Shin - Palisades Park NJ, US
Han Kwang Cho - Hackensack NJ, US

Assignee:

Locus Telecommunications, Inc. - Englewood Cliffs NJ

International Classification:

H04M015/00

US Classification:

3791142, 37911415, 37911416, 37912701, 37912703

Abstract:

The present invention relates to a system and method for providing prepaid telecommunication services. More particularly, prepaid telephone calls can be made by users without entering any access code, if such calls are made from telephone numbers previously registered in the telecommunication system in connection with valid access codes. Prepaid telephone calls can also be made from non-registered telephone numbers after providing the telecommunication system with a valid access code.

US Patent:

6982989, Jan 3, 2006

Filed:

Jun 11, 2001

Appl. No.:

09/878723

Inventors:

Jae Park - Congers NY, US
Roy McNeil - Warwick NY, US
David Delgadillo - Plano TX, US

Assignee:

Fujitsu Limited - Kanagawa-ken

International Classification:

H04J 3/22
H04J 3/24

US Classification:

370471, 370474

Abstract:

A network device transfers variable-length data frames across a synchronous network employing a multiple-channel synchronous transport signal. Encapsulation logic encapsulates each data frame in a point-to-point frame including a body portion of the data frame and a length value located in a beginning portion of the point-to-point frame. Segmentation logic divides each point-to-point frame into fixed-sized segments, a first segment carrying the beginning portion of the point-to-point frame. Transmitting circuitry transmits the frame segments as payloads of at least one channel of the synchronous transport signal, the payloads being marked so as to be identifiable. Receiving circuitry receives payloads of at least one channel of the synchronous transport signal and from each received set of payloads regenerates a corresponding point-to-point frame using the length value from the first segment thereof. De-capsulation logic de-capsulates each regenerated point-to-point frame to recover the corresponding data frame.

US Patent:

7004708, Feb 28, 2006

Filed:

Jul 11, 2003

Appl. No.:

10/618175

Inventors:

Jae Heon Park - Cupertino CA, US

Assignee:

ASML Holding N.V.

International Classification:

B65H 5/00

US Classification:

41422201, 414217, 414937

Abstract:

Systems and methods are described for wafer processin. A wafer processing apparatus includes: a first wafer transporter; a process station coupled to the first wafer transporter, the process station including: a first plurality of wafer processing stacks, each of the plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to the plurality of wafer processing modules, each of the plurality of wafer processing modules adjacent, and accessible by, the second wafer transporter; and a third wafer transporter coupled to the process station, wherein any of the plurality of wafer processing modules in any of the plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters from among the first, second and third wafer transporter. The systems and methods provide advantages from minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization.