Jaideep P Dastidar

US Patent:

7111105, Sep 19, 2006

Filed:

Dec 31, 2001

Appl. No.:

10/038844

Inventors:

Paras Shah - Houston TX, US
Ryan J. Hensley - Dallas TX, US
Jaideep Dastidar - Houston TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

710312, 710313, 710310, 710 29

Abstract:

A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

US Patent:

7139859, Nov 21, 2006

Filed:

Dec 31, 2001

Appl. No.:

10/039130

Inventors:

Jaideep Dastidar - Houston TX, US
Ryan J. Hensley - Houston TX, US
Michael Ruhovets - Houston TX, US
An H. Lam - Houston TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

710306, 710311, 710315

Abstract:

A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

US Patent:

8051303, Nov 1, 2011

Filed:

Jun 10, 2002

Appl. No.:

10/165938

Inventors:

Jaideep Dastidar - Houston TX, US
Joshua Wyde - Houston TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/14
G06F 7/04

US Classification:

713193, 726 16

Abstract:

The disclosed embodiments relate to a secure configuration space for a computing device. Each of the configuration resisters in a configuration space are divided into security bits and configuration data bits. The security bits are assigned a predetermined value. When reading from or writing to a given configuration register, the data in the bit positions corresponding to security bits must match the predetermined values or read/write access is denied.

US Patent:

8473644, Jun 25, 2013

Filed:

Mar 4, 2009

Appl. No.:

12/398103

Inventors:

Sanjay Deshpande - Austin TX, US
Jaideep Dastidar - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 3/00

US Classification:

710 20, 711207

Abstract:

Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e. g. , of operation translations) may be specialized on a per-logical-device basis (or even a per-sub-window basis), thereby offering individual logical I/O devices (or sub-windows thereof) immediate, indexed, and/or untranslated operation mapping frameworks appropriate to their individual requirements or needs.

US Patent:

20020120805, Aug 29, 2002

Filed:

Feb 23, 2001

Appl. No.:

09/792833

Inventors:

Ryan Hensley - Dallas TX, US
Jaideep Dastidar - Houston TX, US
Timothy Waldrop - Austin TX, US

International Classification:

G06F013/36

US Classification:

710/314000

Abstract:

A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

US Patent:

20100228943, Sep 9, 2010

Filed:

Mar 4, 2009

Appl. No.:

12/398099

Inventors:

Sanjay Deshpande - Austin TX, US
Jaideep Dastidar - Austin TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G06F 12/06

US Classification:

711206, 711E12078

Abstract:

Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources.

US Patent:

20100325327, Dec 23, 2010

Filed:

Jun 17, 2009

Appl. No.:

12/486387

Inventors:

Bryan D. Marietta - Austin TX, US
Jaideep Dastidar - Austin TX, US
John Vaglica - Austin TX, US
Mihir A. Pandya - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/36

US Classification:

710240

Abstract:

A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module.

US Patent:

20220292024, Sep 15, 2022

Filed:

May 26, 2022

Appl. No.:

17/826074

Inventors:

- San Jose CA, US
Jaideep DASTIDAR - San Jose CA, US

International Classification:

G06F 12/0891
G06F 3/06
G06F 9/50
G06F 12/0815

Abstract:

The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.