Jalal A Elhusseini

US Patent:

6407949, Jun 18, 2002

Filed:

Dec 17, 1999

Appl. No.:

09/465665

Inventors:

Sanjay Jha - San Diego CA
Stephen Simmonds - San Diego CA
Jalal Elhusseini - Poway CA
Nicholas K. Yu - San Diego CA
Safi Khan - San Diego CA

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

G11C 700

US Classification:

36518533, 36518511, 711105, 711168

Abstract:

The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

US Patent:

20010036109, Nov 1, 2001

Filed:

Mar 26, 2001

Appl. No.:

09/818186

Inventors:

Sanjay Jha - San Diego CA, US
Stephen Simmonds - San Diego CA, US
Jalal Elhusseini - Poway CA, US
Nicholas Yu - San Diego CA, US
Safi Khan - San Diego CA, US

International Classification:

G11C011/34
G06F012/00

US Classification:

365/185330, 711/103000, 711/168000, 711/164000, 711/167000, 711/202000, 713/002000

Abstract:

The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory. Thus, portions of flash memory subject to flash memory degradation may be programmed with a higher number of wait states than portions of memory that are not subject to degradation. In this manner, overall flash memory access times are improved, as compared with systems wherein the wait states for all read access operations are set to accommodate a maximum amount of possible flash memory degradation. The flash memory controller additionally includes a password register providing a separate password for different portions of the flash memory array. Write and erase commands received by the flash controller are only performed if the commands specify a valid password. This helps prevent inadvertent erasure or rewriting of portions of flash memory array as a result of software bugs or the like. A separate, second level password protection is provided in connection with a portion of the flash memory storing a boot loader. A memory swap unit is also provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Initially, the boot loader is stored at a lowest memory address and primary programs are stored at a middle memory address. Upon completion of the operations of the boot loader, the memory space is swapped such that the primary programs are thereafter stored at the lowest memory address to permit expedited access thereto. Method and apparatus implementations are disclosed.

US Patent:

20150349793, Dec 3, 2015

Filed:

Nov 4, 2014

Appl. No.:

14/532264

Inventors:

- San Diego CA, US
Shahin Mehdizad Taleie - San Diego CA, US
Michael Joseph McGowan - Mesa AZ, US
Jenny Kuo - San Diego CA, US
Dongwon Seo - San Diego CA, US
Jalal Ahmad Elhusseini - San Diego CA, US

International Classification:

H03M 1/10
H03M 1/68

Abstract:

A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.