James E Allan

US Patent:

6566952, May 20, 2003

Filed:

Jul 27, 2001

Appl. No.:

09/916925

Inventors:

James D. Allan - Colorado Springs CO

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03F 345

US Classification:

330255, 330253, 330292

Abstract:

An embodiment of an amplifier circuit including a power supply node and an output node is adapted to provide, during operation, an output node voltage ranging to within 0. 2 volts of a power supply voltage used during the operation. An embodiment of the circuit includes a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. In a method of providing an output voltage near the power supply voltage of an amplifier, a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage is produced. The first stage output voltage may further be coupled to a second stage of the amplifier, where the coupling may modulate a current flow through a first pair of cascaded transistors. An output node of the amplifier may be arranged between the pair of transistors and the power supply voltage node.

US Patent:

6510483, Jan 21, 2003

Filed:

Mar 21, 2000

Appl. No.:

09/531365

Inventors:

Stefan-Cristian Rezeanu - Colorado Springs CO
James Allan - Colorado Springs CO
Emad Hamadeh - Santa Clara CA
Eric Gross - Monument CO
Vijay Srinivasaraghavan - Colorado Springs CO
Robert Manning - Monument CO

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1340

US Classification:

710307, 710 51, 710 52, 711211, 36518902, 36523002, 713600

Abstract:

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

US Patent:

7505303, Mar 17, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/644447

Inventors:

Jayant Ashokkumar - Colorado Springs CO, US
David W. Still - Colorado Springs CO, US
James D. Allan - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 11/00

US Classification:

365154, 36518507

Abstract:

A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

US Patent:

7518916, Apr 14, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/644819

Inventors:

Jayant Ashokkumar - Colorado Springs CO, US
David W. Still - Colorado Springs CO, US
James D. Allan - Colorado Springs CO, US
John Roger Gill - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 16/04

US Classification:

36518507, 365154

Abstract:

A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

US Patent:

7539054, May 26, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/644641

Inventors:

Jayant Ashokkumar - Colorado Springs CO, US
David W. Still - Colorado Springs CO, US
James D. Allan - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G11C 16/04

US Classification:

36518507, 36518519

Abstract:

A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

US Patent:

8315096, Nov 20, 2012

Filed:

Aug 24, 2011

Appl. No.:

13/216546

Inventors:

James D Allan - Colorado Springs CO, US
Jayant Ashokkumar - Colorado Springs CO, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 14/00

US Classification:

36518508, 365154, 36518916, 365226

Abstract:

The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

US Patent:

20080151654, Jun 26, 2008

Filed:

Dec 22, 2006

Appl. No.:

11/644165

Inventors:

James D. Allan - Colorado Springs CO, US
Jayant Ashokkumar - Colorado Springs CO, US

International Classification:

G11C 7/20
G11C 7/12

US Classification:

36518916

Abstract:

A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

US Patent:

45815461, Apr 8, 1986

Filed:

Nov 2, 1983

Appl. No.:

6/547971

Inventors:

James D. Allan - Colorado Springs CO

Assignee:

Inmos Corporation - Colorado Springs CO

International Classification:

H03K 3354
G05F 156

US Classification:

307297

Abstract:

A CMOS substrate bias generator including a PMOS charge pump and a regulator for controlling the operation of the substrate bias generator. The substrate bias generator further includes an input circuit, a reference circuit to provide a reference voltage, a comparison circuit to compare voltage levels between the input and the reference circuit, and output circuitry to provide a signal from the comparison circuitry to the substrate bias generator. The comparison circuitry further includes hysteresis circuitry tending to preserve voltage at a node in the comparison circuit despite an imbalance between the input circuit and the reference circuit.